Showing papers on "Fault coverage published in 1976"

Fault-Tolerant Systems

Abstract: Basic concepts, motivation, and techniques of fault tolerance are discussed in this paper. The topics include fault classification, redundancy techniques, reliability modeling and prediction, examples of fault-tolerant computers, and some approaches to the problem of tolerating design faults.

A Logic System for Fault Test Generation

Abstract: This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propagtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.

A Module-Level Testing Approach for Combinational Networks

Abstract: A module-level testing approach for combinational networks which employs hardware modification and a simplified test generation procedure is described. The approach is based on a directed graph model for the network derived at the module level. The objectives of the approach are to deal with testing directly at the module level, to use cataloged tests for the modules in the network environment, and to generate a fault detection test set with "good" fault location capability. Networks which consist of single-output modules are treated initially and then the results are extended to networks which consist of multiple-output modules. Hardware modification and test generation procedures are illustrated.

An Integrated Circuit Fault Model for Digital Systems.

Abstract: : A model for the faulty behavior of digital networks realized using integrated circuit devices is proposed This model, the pin fault assumption, is based on a study of the most frequently encountered failure mechanisms for such networks, and the observation that previous fault assumptions model a large number of faults which occur with low frequency The basis for the pin fault model, and an investigation of multiple fault detection using this model are presented Fault detection for combinational modules is investigated, and it is shown that multiple pin fault detection test sets for such modules may be quite easily generated The computation required to generate such test sets is independent of the circuit realization internal to the model, and each test generated requires about the same amount of computation The computational complexity of test generation is greatly reduced compared to that for previously studied fault models Pin fault detection experiments for sequential machines are studied, and methods for designing such experiments are developed These design methods are compared to those under other fault assumptions, and a substantial reduction is observed in the length of such sequences and the computation required to produce them (Author)

Fault Detection Problems and their Impact on the Design of Digital Circuits

Abstract: This communication presents the principal methods for detecting faults in logical structures. As a consequence of their limitations (size of the structures) methods for modifying the circuits in order to obtain easily testable and/or self-checking systems are given.