Showing papers on "Fault coverage published in 1979"

Detection of Faults in Programmable Logic Arrays

Abstract: A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required by exhaustive testing. Finally, it is shown that many interesting classes of multiple faults are also detected by the test sets.

Simplified ATPG and analog fault location via a clustering and separability technique

Abstract: Automatic test program generation (ATPG) for analog system fault location is considered and a procedure for generating a set of tests for a linear network using gain and phase measurements from input-output measurements only is presented. The best subset of features for fault diagnosis is selected via a discriminatory index. Each feature subset selected during the optimization procedure is tested for enhanced separability of observation space for faults and the efficiency of the subset for diagnosis is indexed using a confidence level. The fault matrix formed using the selected feature subset is analized for cluster formation, the separability measure introduced is used to group the fault cases and a reduction of the cases to be considered on-line is obtained. In fault location, a fault is identified to a specific group which then is further located to the individual component and is carried out for varying production tolerances.

Multiple Fault Diagnosis in Combinational Networks

Abstract: The concept of prime faults is introduced for the study of multiple fault diagnosis in combinational logic networks. It is shown that every multiple fault in a network can be represented by a structurally equivalent fault with prime faults as its only components. Functional and structural masking and covering relations among faults are defined. These relations can be exploited to greatly simplify multiple fault analysis and their test generation. We present an efficient algorithm that generates a multiple fault detection test set and identifies redundancies. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are also included.

On Necessary and Sufficient Conditions for Multiple Fault Undetectability

Abstract: This correspondence states necessary and sufficient conditions for a multiple stuck-at fault in a combinational network to be undetected by a test set. The conditions are given in terms of fault masking relationships. It is shown that several other statements on this subject which have appeared in the literature are invalid.

On Analytical Modeling of Intermittent Faults in Digital Systems

Abstract: This correspondence discusses three analytical models for intermittent faults in digital systems. These models attempt to represent the stochastic behavior of intermittent faults accurately. The models find applications in predicting the performance of fault detection algorithms. A fault detection procedure is described and its performance is examined based on the analytical models. A numerical example is presented which illustrates the performance prediction of the fault detection algorithm.

Microprocessor architecture for improved chip testability

Abstract: An improved architecture for a single chip microprocessor CPU includes provision for directly observing at its terminals the control signals from its instruction decoder to facilitate functional testing of the chip. The CPU, upon receiving a command signal transfers the signals on the control lines of its instruction decoder to its output terminals. In one embodiment of the invention the command signal is applied to the CPU chip at a designated input terminal. In another embodiment, the command signal is applied through a special instruction. The improvements permit increased functional test fault coverage and shorter test programs.

A pragmatic approach to automatic test generation and failure isolation of analog systems

Abstract: Digital automatic test generation has been successful due to simplified modeling at the logic gate or higher level, rather than the component level, and to logic simulation performed for the stuck-at failure mode only. Analog automatic test generation generally requires modeling and simulation at the component level and continuous failure modes over a certain range of parameter values. As a result, most analog automatic test generation and fault isolation techniques demand a large computational capability on the ATE or off-line computers. Any practical analog automatic test generation solution must eventually address this problem. All analog automatic test generation techniques presently under investigation assume the availability of all or certain designated nodes as test points for stimulus injection and/or response measurement. This assumption suggests the possibility of GO-NO-GO tests to fault isolate to a "primitive," which may contain several circuit components. The "complementary signal" design suggested by Schrelher, appears well suited for providing an effective GO-NO-GO test; the signal and its response are determined by the poles and zeros of the circuit.

Design Of A Fault-Tolerant Microprocessor

Abstract: Following an overview of the general practice in the reliable design of digital systems and the discussion of those design considerations for selfchecking and fault tolerant machines, the Self- Checking Microprocessor proposed by Maki (3) is brought to the readers' attention. Then the posibility of using this self-checking design in a hybrid-redundant microprocessor system is explored. In this paper, the self-checking processor and the main memory unit are triplicated for the purposeof error detection and momentary fault masking. Reconfiguration, allowing stand by units to replace failed unit, is possible due to the intelligence of the individual processors. Similarly the memory modules can be switched ON/OFF line by an additional self-checking processor incorporated into the design assuming the task of the majority voter of this TMR system.

On-line Fault Detection And Correction In Microprocessor Systems

Abstract: In most on-line diagnostic schemes whenever a fault is detected in a system, a rather involved system recovery routine is initiated irrespective of whether the fault is caused by a failure inside a chip, or by a failure outside a chip, say, on the bond connecting a pin to the chip. Failures of the latter type cause errors only when some information is being transferred from one chip to another chip. In this paper, 'two new techniques to system recovery are described for the case when an error is on any such data transfer path. These schemes are implementable locally, and the system is ensured to recover from any single stuck-at fault, single AND-bridge fault, or single OR-bridge fault in a single retry. The system- recovery from faults internal to chips can be per- formed using sophisticated routines. Thus, two- level approach to on-line system diagnosis seems to be more efficient.

Trends in reliability modeling technology for fault tolerant systems

Abstract: Reliability modeling for fault tolerant avionic computing systems was developed. The modeling of large systems involving issues of state size and complexity, fault coverage, and practical computation was discussed. A novel technique which provides the tool for studying the reliability of systems with nonconstant failure rates is presented. The fault latency which may provide a method of obtaining vital latent fault data is measured.

Recursive Coverage Projection of Test Sets

Abstract: In the generation of test sets for the detection of stuck-type faults in combinational switching networks, it is an expedient and reasonably common assumption to consider explicitly faults only of specified sizes (for example, all single faults), and then to assume (or hope) that most or all faults of larger sizes will be covered (that is, detected) as well. This paper systematically addresses this aspect of multiple fault coverage in a quantitative manner for combinational networks, wherein only primary input fanout is allowed. A procedure is given to estimate (or project) the multiple fault coverage capability of a test set based on the known coverage capability of that test set for subsets of the multiple faults. This is accomplished by means of a recursive use of a detailed formula which exploits two fundamental interrelationships between test sets and faults. Based upon these results, it can be shown that the above-mentioned assumption must be made, in general, with discretion as its validity is highly network structure/test set dependent.

Application of pattern recognition techniques to fault tolerant software systems

Abstract: Inference techniques are applied to computing systems to improve the allocation of resources for fault tolerant performance. Using a general model for such systems, the influence of estimation errors for system parameters on the resulting system fault performance is examined. These results are then applied to the problem of error mode testing-finding the underlying error structure of the system. Simulation is used to illustrate the properties discussed.

Comments on "Multiple Fault Detection in Combinational Network"

Abstract: In the above paper,1the authors have defined complete test, closed fault set, fault set graph, and undetected fault set as follows.