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Showing papers on "Fault coverage published in 1980"


Journal ArticleDOI
TL;DR: In this paper, a general graph-theoretic model is developed at the register transfer level which takes the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model.
Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

380 citations


Journal ArticleDOI
TL;DR: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to Check response times under nominal operating conditions, and 3) functional tests toCheck its logical behavior.
Abstract: At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.

350 citations


Journal ArticleDOI
TL;DR: Researchers have established and extended a model for system-level fault diagnosis that is applicable to large multiprocessor networks and helps clarify the role of memory in system fault diagnosis.
Abstract: Large multiprocessor networks require system-level fault diagnosis. Researchers have established and extended a model for such diagnosis.

93 citations


Journal ArticleDOI
TL;DR: There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.
Abstract: The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

72 citations


Proceedings ArticleDOI
23 Jun 1980
TL;DR: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: is applicable to both single and multiple faults, does not require fault enumeration, and can identify faults which prevent initialization.
Abstract: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.

67 citations


Journal ArticleDOI
TL;DR: Modular systems employing building-block VLSI circuits may provide fault tolerance to a variety of applications.
Abstract: Modular systems employing building-block VLSI circuits may provide fault tolerance to a variety of applications.

61 citations


Journal ArticleDOI
Agarwal1
TL;DR: This paper develops a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA, and shows that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in aPLA.
Abstract: The increasing recognition of PLA's as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA's is the class of contact faults. A single contact fault is the spurious presence or absence of a contact between a row and a column of a PLA. We consider in this paper the problem of determining the capability of complete single contact fault test sets to cover multiple contact faults of PLA's. Our approach consists of developing a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA. Using this model, it is shown that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in a PLA. Applications of this model to stuck-at fault diagnosis are also discussed.

61 citations


Patent
08 Feb 1980
TL;DR: In this paper, the present invention comprises computer system equipment useful for detection of faults in data transmission within a computer system by monitoring the current flow through a digital signal source means, which is characterized in that it only draws significant current during a non-transition period when a fault condition occurs.
Abstract: The present invention comprises computer system equipment useful for detection of faults in data transmission within a computer system. Fault detection is accomplished by monitoring the current flow through a digital signal source means, which is characterized in that it only draws significant current during a non-transition period when a fault condition occurs.

28 citations


Journal ArticleDOI
Akers1
TL;DR: Test generation procedures are rooted in the SSI/MSI era, but new techniques will cope with today's vastly more complicated LSI/VLSI systems.
Abstract: Existing test generation procedures are rooted in the SSI/MSI era. New techniques will cope with today's vastly more complicated LSI/VLSI systems.

19 citations


Journal ArticleDOI
Agarwal1, Masson
TL;DR: The basis of this approach is the development of a generic perspective to multiple faults which uses a representation of such faults called an L-expression which leads to a technique for obtaining the greatest lower bound on the multiple fault coverage capability of an SFDTS by means of a simple table look-up process.
Abstract: Given any combinational, internal fan-out-free network and any complete single fault detection test set (SFDTS) for the network, we consider in this paper the problem of determining the minimal extent to which that SFDTS will cover multiple faults in the network. The basis of our approach is the development of a generic perspective to multiple faults which uses a representation of such faults called an L-expression. This perspective leads to a technique for obtaining the greatest lower bound on the multiple fault coverage capability of an SFDTS by means of a simple table look-up process. In addition to generalizing previously known results regarding multiple fault coverage, two particularly interesting results obtained from this approach are as follows: 1) On the average, every SFDTS for an internal fan-out-free network covers 92 percent of all multiple faults of sizes 8 and less. 2) On the average, every SFDTS for an internal fan-out-free network covers at least 46.1 percent of all multiple faults.

16 citations


Patent
30 May 1980
TL;DR: In this article, a fault cause tree is used to analyze the cause of a fault in a fault detection system and the change of data before the fault is detected in the occurrence of the fault.
Abstract: PURPOSE:To treat a fault effectively while relieving an operator from the load of investigating the cause, by obtaining information effective to the investigation on the cause of the fault from the change of data before the fault is detected in the occurrence of the fault. CONSTITUTION:Data of each plant up to the detection of a fault by a fault detector 3 is stored previously as a fault cause tree 10, and a data change table 9 containing the tree 10 and the change of data before the fault is detected, and a secular value table 8 recording data in the detection of the fault are used to analyze the cause of the fault. Then, a fault cause deciding device 6 analyzes the cause of the fault from the tree 10 and the result of it is displayed 7. Here, the tree is displayed to display the change and path of the plant data understandably. Since the time when the data changed is also stored in the table 9, it is displayed simultaneously. Consequently, a plant fault is treated rapidly and adequately.

Journal ArticleDOI
TL;DR: In this paper, a method of locating a single fault in a linear analogue system by determining the consistency of the inaccessible nodal voltage vectors is proposed, which does not require the assumption of an invariable sensitivity matrix, and can thus be applied to catastrophe faults as well.
Abstract: A method of locating a single fault in a linear analogue system by determining the consistency of the inaccessible nodal voltage vectors is proposed. It does not require the assumption of an invariable sensitivity matrix, and can thus be applied to catastrophe faults as well.

Proceedings ArticleDOI
Samiha Mourad1
23 Jun 1980
TL;DR: A hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur, is described, which introduces a new definition of fault coverage and allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.
Abstract: This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.

Proceedings ArticleDOI
23 Jun 1980
TL;DR: The design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator is described and incorporated as a standard feature in the latest release of the ISPS simulator.
Abstract: Fault tolerance is an important attribute of most computer systems, and to be effective it must be an explicit objective from the beginning of the design process. Inserting faults into a simulation of the machine and observing its behavior is a thorough and economical technique for evaluating prospective fault detection, diagnosis, recovery, and repair mechanisms. As systems become larger due to rising semiconductor integration, the expense of these fault simulations increasingly necessitates that they be performed at higher levels of abstraction (such as the register transfer level) rather than lower (such as the gate level). This can achieve major cost savings without significantly compromising fault coverage. This paper describes the design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator. The ISPS simulator was chosen because it is an interactive, high level simulator which is capable, mature, and widely used and accepted. The faults which can be simulated include hard and transient, deterministic and probabilistic, stuck-at and bridged, data, control, and operation types. These facilities have been implemented and demonstrated to be sound in both concept and implementation. They have been incorporated as a standard feature in the latest release of the ISPS simulator.

Journal ArticleDOI
Coy1
TL;DR: It is shown that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of Tests is sufficient for a complete multiple fault detection test set.
Abstract: Poage has constructed a complex fault detection algorithm which generates a complete and minimal test set of all multiple stuck-at faults of a given combinational network. Several authors have derived from his method fast and simple multiple fault detection algorithms, which are claimed to generate complete test sets with a "near-minimal" or "near-optimal" number of tests. We show that the algorithms by Bossen and Hong and the algorithm by Yang and Yau may generate test sets with an exponential number of tests (relative to the number of inputs) where a linear number of tests is sufficient for a complete multiple fault detection test set.

DOI
01 Jul 1980
TL;DR: The new concept of performability, which combines both the performance and the reliability of a system, and the configuration optimisation of a gracefully degradable computing system are discussed.
Abstract: A fault-tolerant computing system performs its intended functions irrespective of the occurrence of certain failures. As the system becomes more and more reliable with built-in fault-tolerance, its analysis, validation and comparison with another system become formidable tasks. Such a study involves issues such as fault classification, figures of merit, fault-tolerant architectures, coverage estimation and automated methods of reliability evaluation. This paper provides a comprehensive survey of all these topics. The new concept of performability, which combines both the performance and the reliability of a system, and the configuration optimisation of a gracefully degradable computing system are also discussed.

Journal ArticleDOI
TL;DR: In this paper, a method is developed for obtaining a highly compressed fault table for two-level combinational circuits, where a set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault tables.
Abstract: A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.