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Showing papers on "Fault coverage published in 1983"


Journal ArticleDOI
E. B. Eichelberger1, E. Lindbloom1
TL;DR: Embedded linear feedback shift registers can be used for logic component self-test and a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis is given.
Abstract: Embedded linear feedback shift registers can be used for logic component self-test. The issue of test coverage is addressed by circuit modification, where necessary, of random-pattern-resistant fault nodes. Also given is a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature analysis.

204 citations


Journal ArticleDOI
TL;DR: An overview of the problem of testing semiconductor random access memories (RAMs) and several fault models, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults are presented.
Abstract: This paper presents an overview of the problem of testing semiconductor random access memories (RAMs). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several fault models are &scussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults, and single-cell pattern-sensitive faults. Test procedures for these fault models are presented and their fault coverage and execution times are discussed. The paper is intended for the general computer scmnce audience and presupposes no background in the hardware testing area.

189 citations



Journal ArticleDOI
TL;DR: A concept of k-node-fault testability is introduced and a sufficient and almost necessary condition for testability as well as the test procedure is presented, which depends only on the graph of the circuit, not on the element values.
Abstract: A concept of k -node-fault testability is introduced. A sufficient and almost necessary condition for testability as well as the test procedure is presented. This condition is further evolved to a necessary and almost sufficient topological condition for testability. A unique feature of this condition is that it depends only on the graph of the circuit, not on the element values. Based on this condition, a design of testability can be established.

90 citations


Patent
John W. Maher1
09 Dec 1983
TL;DR: In this article, a system and a method for isolating faults and recovering a distributed system of the type including a plurality of modules to optimized operation is disclosed, at least some of the modules are active fault recovery modules and include fault detecting means for initializing a fault check routine and sensing faults within the distributed system.
Abstract: There is disclosed a system and a method for isolating faults and recovering a distributed system of the type including a plurality of modules to optimized operation. At least some of the modules are active fault recovery modules and include fault detecting means for initializing a fault check routine and sensing faults within the distributed system. Voting means are associated with each active module for placing a vote during each fault check routine in response to a detected fault. Collective vote determining means record the votes of the active modules after each fault check routine and recovery sequence initializing means initializes a fault isolation and recovery sequence in response to a given number of consecutive collective votes exceeding a predetermined value.

40 citations


Patent
31 Oct 1983
TL;DR: In this article, the authors describe a system for handling detected error signals, providing the circuit elements for processing fault reports and implementing automatic fault isolation, which applies to all design levels, from the unit itself to individual components of which it is comprised.
Abstract: The present disclosure describes a system for handling detected error signals, providing the circuit elements for processing fault reports and implementing automatic fault isolation. More specifically, the system develops a fault report for each component based upon error signals derived therefrom. Changes in the fault report are detected and selector circuits are actuated to automatically isolate the fault to the particular component or components, or to reset the system in response to previous fault correction. The present system is advantageous in that it is independent of the equipment technology and applies to all design levels, from the unit itself to the individual components of which it is comprised.

39 citations


01 Jan 1983
TL;DR: The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated and an extensive, 3-axis, high performance control computation was added.
Abstract: The results of fault injection experiments utilizing a gate-level emulation of the central processor unit of the Bendix BDX-930 digital computer are described. Several earlier programs were reprogrammed, expanding the instruction set to capitalize on the full power of the BDX-930 computer. As a final demonstration of fault coverage an extensive, 3-axis, high performance flght control computation was added. The stages in the development of a CPU self-test program emphasizing the relationship between fault coverage, speed, and quantity of instructions were demonstrated.

26 citations


Proceedings ArticleDOI
01 Jan 1983
TL;DR: The summary presented stresses that a self-test program should be designed to capitalize on the hardware mechanization of the processor, if this is not done, subtests tend to repeatedly exercise the same hardware components while neglecting to exercise a substantial proportion of the remainder.
Abstract: Studies carried out by McGough and Swern (1981, 1983) are summarized. In these studies, an avionics processor was simulated and a series of fault injection experiments was carried out to determine the degree of fault latency in a redundant flight control system that employed comparison monitoring as the exclusive means of failure detection. A determination was also made of the fault coverage of a typical self-test program. The summary presented stresses that a self-test program should be designed to capitalize on the hardware mechanization of the processor. If this is not done, subtests tend to repeatedly exercise the same hardware components while neglecting to exercise a substantial proportion of the remainder. It is also pointed out that fault latency is relatively independent of both the length and instruction mix of a program. A significant difference is found in fault coverage assessed using pin-level and gate-level fault models.

21 citations


Journal ArticleDOI
TL;DR: In this article, the authors deal with problems concerning fault modelling for LSI/VLSI devices, and different fault classes are discussed for each, including stuck-at, bridging, functional and time-dependent faults.
Abstract: The review paper deals with problems concerning fault modelling for LSI/VLSI devices. Both random and regular logic are considered, and different fault classes are discussed for each, including stuck-at, bridging, functional and time-dependent faults. Specific fault models are then considered for microprocessors, RAMs and PLAs

16 citations


Journal ArticleDOI
TL;DR: Tests good for SSI and MSI circuits can't cope with the complexity of LSI, so new techniques for test generation and response evaluation are required.
Abstract: Tests good for SSI and MSI circuits can't cope with the complexity of LSI. New techniques for test generation and response evaluation are required.

16 citations


Proceedings ArticleDOI
K. E. Torku1, Charles E. Radke1
27 Jun 1983
TL;DR: A fault model for each stage of assembly of the package is assumed and the contribution of each of these stages to the quality level is assessed to produce the required relationship to test coverage achieved through test generation programs.
Abstract: A relationship between the quality level of a multichip module package and test coverage is established. A fault model for each stage of assembly of the package is assumed and the contribution of each of these stages to the quality level is assessed to produce the required relationship to test coverage achieved through test generation programs.

Patent
27 May 1983
TL;DR: In this paper, the authors propose to detect assuredly the presence or absence of a fault by storing all normal working states during a cycle of a sequence machine and comparing these working states with a memory every time the working state of the sequence machine varies.
Abstract: PURPOSE: To detect assuredly the presence or absence of a fault by storing all normal working states during a cycle of a sequence machine and comparing these working states with a memory every time the working state of the sequence machine varies. CONSTITUTION: The working state of a sequence machine A is fetched to a fetching means B for each change of said working state. While a memory means C stores previously all normal working states during a cycle of the machine A. A comparing means D compares the data of the means C with that of the means B. When the coincidence is obtained from this comparison, it is decided that the machine A is normally working. While a fault is decided when no coincidence of comparison is obtained. Then a fault signal is delivered to detect early the fault. Thus it is possible to detect a fault early by a simple device and to recover the fault in a short time. This improves the working efficiency of a fault diagnosing device. Such a device is suitable used to a lift, conveyor, etc. COPYRIGHT: (C)1984,JPO&Japio

01 Jan 1983
TL;DR: The use of self-checking nodes and links for implementing fault-tolerant VLSI multicomputers is proposed and it is possible to implement a self-testing comparator which will produce an error indication if the comparator incurs any single physical defect.
Abstract: The use of self-checking nodes and links for implementing fault-tolerant VLSI multicomputers is proposed. The system consists of a large number of VLSI computers interconnected by high-speed dedicated links. Hardware which performs error detection is combined with system-level protocols which handle error recovery and fault treatment. The self-checking nodes notify the rest of the system when their output is erroneous. In order to achieve high fault coverage, error detection is accomplished by duplication and matching. The critical circuit in this scheme is a comparator, which must not be susceptible to faults which can remain undetected and later mask the failure of the functional modules. With both NMOS and CMOS technologies it is possible to implement a self-testing comparator which will produce an error indication if the comparator incurs any single physical defect. 13 references.


Journal ArticleDOI
TL;DR: An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA) and functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests.
Abstract: An on-line algorithm is developed for the location of single cross point faults in a PLA (FPLA). The main feature of the algorithm is the determination of a fault set corresponding to the response obtained for a failed test. For the apparently small number of faults in this set, all other tests are generated and a fault table is formed. Subsequently, an adaptive procedure is used to diagnose the fault. Functional equivalence test is carried out to determine the actual fault class if the adaptive testing results in a set of faults with identical tests. The large amount of computation time and storage required in the determination, a priori, of all the fault equivalence classes or in the construction of a fault dictionary are not needed here. A brief study of functional equivalence among the cross point faults is also made.

Journal ArticleDOI
Oikonomou1, Kain
TL;DR: A fault detection procedure is developed, which is probabilistic because of nondeterminism in the simplified node model, and how to select model abstractions to lower the number of undetectable errors is shown.
Abstract: We introduce a scheme for passive node-level fault detection in a distributed system. With each system node associate a low-cost, low-complexity observer which monitors the pattern of incoming and outgoing messages and compares it against an abstracted model of the node's behavior. We develop a fault detection procedure, which is probabilistic because of nondeterminism in the simplified node model. Abstraction reduces model complexity, but renders some errors undetectable by the observer. In the paper we characterize these undetectable errors. Succeeding studies show how to select model abstractions to lower the number of undetectable errors.


Proceedings ArticleDOI
27 Jun 1983
TL;DR: A new approach to the production testing of VLSI circuits is presented, which achieves 100% single stuck-at fault coverage with under 20 test vectors and no search.
Abstract: We present a new approach to the production testing of VLSI circuits. By using very structured design for testability, we achieve 100% single stuck-at fault coverage with under 20 test vectors and no search. The approach also detects most multiple faults.

Dissertation
01 May 1983

Journal ArticleDOI
Miczo1
TL;DR: A fault detect mechanism is described for hardwired control logic which takes advantage of inherent redundancy in the control logic design style which assigns a unique flip-flop to each machine state.
Abstract: A fault detect mechanism is described for hardwired control logic. The mechanism takes advantage of inherent redundancy in the control logic design style which assigns a unique flip-flop to each machine state. The mechanism is capable of detecting all single stuck-at faults, as well as many multiple faults and intermittents within the control section.

Proceedings ArticleDOI
01 Jan 1983
TL;DR: In this article, the design of a fail-safe LSI circuit for train control applications based on bit-serial, time-sharing and frequency domain operation, as well as a layout method to restrict possible MOS failure modes is discussed.
Abstract: Fault-tolerant design techniques, which have resulted in the development of a fail-safe LSI circuit for train control applications, will be discussed. The design is based on bit-serial, time-sharing and frequency domain operation, as well as a layout method to restrict possible MOS failure modes.

01 Mar 1983
TL;DR: Performance of deductive fault simulation, implemented in ADLIB-SABLE, shows that for sequential as well as combinational circuits, the CPU time increases linearly with increasing number of components simulated, an advantage over fault simulators which simulate one fault at a time and display a quadratic behavior.
Abstract: This technical report presents work in the area of deductive fault simulation. This technique, one of the three fault simulation techniques discussed in the literature, has been implemented in ADLIB-SABLE, a hierarchical multi-level simulator designed and used at Stanford University. Most of the fault models illustrated in this report consider only two fault types: single stuck-at-0 and single stuck-at-Z (high impedance). Gate level fault models have been built for most commonly used gates. The ability to model the fault behavior of functional blocks in ADLIB-SABLE is also demonstrated. The motivation is that for many functional blocks, a gate level description may not be available or that the designer wishes to sacrifice detailed analysis for a higher simulation speed. Functional fault models are built for many commonly used blocks, using a decomposition technique. The ratio of functional fault simulation speed to gate level fault simulation speed has been observed to be of the order of 5 for the typical functional block sizes considered. The ratio however, is not the upper limit and will be larger for larger-sized functional blocks. It was also proved that the functional fault models are invariant with respect to the internal implementation details. A design discipline for sequential circuits is worked out which allows deductive fault simulation. Extensions to the simple (0,1) deductive techniques are studied and the fault models built in the extended domain are observed to be useful in modelling gates of some technologies. A comparison between deductive and concurrent fault simulation methods is given. Performance of deductive fault simulation, implemented in ADLIB-SABLE, shows that for sequential as well as combinational circuits, the CPU time increases linearly with increasing number of components simulated, an advantage over fault simulators which simulate one fault at a time and display a quadratic behavior.

01 Aug 1983
TL;DR: The combined fault characterization and retry decision, in which the characteristics of fault are estimated simultaneously with the determination of the optimal retry policy were carried out, and two solution approaches were developed.
Abstract: A new method to determin an optimal retry policy and for use in retry of fault characterization is presented. An optimal retry policy for a given fault characteristic, which determines the maximum allowable retry durations to minimize the total task completion time was derived. The combined fault characterization and retry decision, in which the characteristics of fault are estimated simultaneously with the determination of the optimal retry policy were carried out. Two solution approaches were developed, one based on the point estimation and the other on the Bayes sequential decision. The maximum likelihood estimators are used for the first approach, and the backward induction for testing hypotheses in the second approach. Numerical examples in which all the durations associated with faults have monotone hazard functions, e.g., exponential, Weibull and gamma distributions are presented. These are standard distributions commonly used for modeling analysis and faults.

Proceedings ArticleDOI
13 Jun 1983
TL;DR: A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array.
Abstract: This paper proposes a microdiagnostic procedure for efficient fault diagnosis of bit-slice processors that are formed by an array of identical bit-slice processors. A test generation procedure for testing the entire array simultaneously instead of testing single slice, one after another, is presented, which is based on the high functional fault model and restricted multiple slice fault assumption within an array. Fault detection and fault location procedures using the generated test sequence are also presented. Using these procedures, a test microprogram and diagnostic system for the bit-sliced processor constructed by the array of four Am 2901 bit-slices are developed.

01 Jan 1983
TL;DR: The main idea is to establish the existence of multiple control paths simultaneously in order to excite more than one behavioral mode at the target submodule using the same paths repeatedly.
Abstract: The principles of Controllability and Observability have been known for Linear Systems for some time. In this thesis similar concepts are shown to be very useful in Digital Test Set Generation. In effect the control of a gate (or submodule) can be achieved by exciting a behavioral mode of this subunit from the primary inputs. Also to insure fault detection, we must guarantee that the response to this excitation is observable at a circuit's output. The method presented in this thesis is an extension of Roth's D-Algorithm which we call the Subscripted D-Algorithm. This algorithm has the property that it can generate many test patterns simultaneously for multiple input submodules. In effect the main idea is to establish the existence of multiple control paths simultaneously in order to excite more than one behavioral mode at the target submodule using the same paths repeatedly. Under the most favorable circumstances all of these modes are checked at once. This is due to the fact that the Subscripted D-Algorithm uses a new kind of D-cube called Subscripted D-Cube. The net effect is felt not only at the submodule under test but also throughout the circuit thereby affecting fault coverage computations. Most faults located on or near the established control and observation paths are detectable without effort. It is also shown that a relatively high number of faults can in general be detected by every test pattern derived using this new method. The Subscripted D-Algorithm reaches a high percentage of fault coverage much faster than the D-Algorithm. Another advantage is that fewer test patterns are needed than the number of test patterns required by the D-Algorithm. Results are shown for circuits with a large number of gates and high fanout.

Journal ArticleDOI
TL;DR: As the use of online systems for transaction processing increases, so does the need for reliable, fault tolerant systems that isolate the end user and the database from the effects of internal hardware faults.

Journal ArticleDOI
TL;DR: In this paper, a test set was developed that placed a controlled ground fault on the system and measured current magnitude and tripping time, which revealed discrepancies that would not have been discovered following more conventional test methods.
Abstract: Performance testing of a ground fault protection system has traditionally been accomplished by simulating high level fault magnitudes at current transformer secondary. For a new chemical manufacturing facility, a procedure was devised to safely stage ground faults on the 480-V distribution system. To implement the procedure, a test set was developed that placed a controlled ground fault on the system and measured current magnitude and tripping time. Tests were conducted without the need to modify the distribution system or the ground protection wiring in any way. This feature revealed discrepancies that would not have been discovered following more conventional test methods.