Showing papers on "Fault coverage published in 1992"

CRIS: a test cultivation program for sequential VLSI circuits

Abstract: This paper discusses a novel approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handed, and both stuck-at and transistor faults are handle accurately. The approach has been implemented in a hierarchical test generation system, CRIS, that runs under UNM on SPARC workstations. CRIS has been used successfully to generate tests with high fault coverage for large combinational and sequential circuits.

The Effectiveness of IDDQ, Functional and Scan Tests: How Many Fault Coverages Do We Need?

Abstract: This paper addresses the issue of achieving high quality by quantifying fault coverages for a number of different types of faults. Firstly it is shown how coverage requirements become more stringent with increasing chip area. Data is then presented from a production part tested with IDDO, scan, timing and fuxtional tests. Three different coverage metrics are considered for the IDDQ tests and the relative effectiveness of the different components of the full test suite are analyzed. It is demonstrated that no component can be removed without suffering a reduction in quality.

CRIS: A test cultivation program for sequential VLSI circuits

Abstract: An approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels is discussed. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses a hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handled, and both stuck-at and transistor faults are handled accurately. The approach was implemented in a hierarchical test generation system, CRIS, that runs under UNIX on SPARC workstations. CRIS was used successfully to generate tests with high fault coverage for large combinational and sequential circuits. >

Skewed-Load Transition Test: Part II, Coverage

Abstract: A skewed-load transition test is a delay test where the second vector of the delay test pair is a one bit shift over the first vector in the pair. This situation occurs when testing the combinational logic residing between scan chains. This paper concentrates on the issue of coverage in skewed-load transition test. A topological lower bound of the transition test coverage is derived. This bound is shown to work well for the entire family if ISCAS combinational circuits. It is also shown that input ordering plays a key role in the attainable transition fault coverage. The paper describes a heuristic for input ordering that will achieve a nearly optimal transition fault coverage.

Test generation by environment emulation

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

HOPE: an efficient parallel fault simulator

Abstract: The authors present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. HOPE is a parallel fault simulator based on single fault propagation. It adopts the zero gate delay model. The key idea incorporated in HOPE is to screen out faults with short propagation paths, and prevent them from being simulated in parallel. The screening process drastically reduces the number of faults simulated in parallel to achieve substantial speedup. The experimental results presented show that HOPE is about two times faster than PROOFS for most ISCAS89 sequential benchmark circuits. >

The multiple observation time test strategy

Abstract: The authors consider the test generation problem, for synchronous sequential circuits in the case where hardware reset is not available (or cannot be assumed to be fault free). It is shown that the conventional testing approach, in which a fault is detected at a single predetermined time unit along the test sequence and in which the response of the circuit under test is compared against a single fault-free response, valid for all initial states of the circuit, can cause detectable faults to be declared undetectable. The use of a small number of different observation times and a small number of fault-free responses can allow the fault to be detected. Based on this observation, the use of multiple fault free responses and multiple time units for observation of the response of the circuit under test is suggested and test generation algorithms under the multiple observation time test strategy are given. Experimental results demonstrate the effectiveness and practicality of the multiple-observation-time strategy in increasing the fault coverage. >

I DDQ testing as a component of a test suite: the need for several fault coverage metrics

Abstract: This article is concerned with the role of I DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with Iddq scan, timing and functional tests. To realistically fault grade I DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total Iddq failures (parts which fail Iddq regardless of whether they fail other tests as well) or unique IDdq failures (parts which fail only Iddq). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.

On the generation of small dictionaries for fault location

Abstract: Fault location based on a fault dictionary is considered. To justify the use of a precomputed dictionary in terms of computation time, the computational effort invested in computing a dictionary is first analyzed. The number of circuit diagnoses that need to be performed dynamically, without the use of precomputed knowledge, before the overall effort exceeds the effort of computing a dictionary, is studied. Experimental results on ISCAS85 circuits show that for relatively small numbers of diagnoses, a precomputed dictionary is more efficient. A method to derive small dictionaries without losing resolution of modeled faults is then proposed. Methods to compact the resulting dictionary further, using compaction techniques generally applied to fault detection, are then described. Experimental results are presented to demonstrate the effectiveness of the methods presented. Internal observation points to increase the resolution of the test set are also considered.

Diagnostic Fault Simulation of Sequential Circuits

Abstract: In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

ROTCO: a reverse order test compaction technique

Abstract: In this paper, the authors consider the problem of reducing the test set sizes for single stuck-at faults in combinational logic circuits. They report on an alternative to the conventional reverse order fault simulation, called reverse order test compaction (ROTCO). The proposed procedure processes a test set obtained by an existing test generator, with the sim of reducing the test set size. Unlike reverse order fault simulation, the proposed procedure allows the test vectors to be changed in order to increase the flexibility in detecting faults detected by earlier vectors, thereby potentially removing tests that cannot be removed by reverse order fault simulation. Experimental results for ISCAS-85 and PLA benchmark circuits are presented to demonstrate the effectiveness of the proposed procedure. >

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method for estimating the coverage of path delay faults of a given test set, without enumerating paths, is proposed The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed Experimental results to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage are presented Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures that are based on enumeration of paths >

An effective BIST scheme for ROM's

Abstract: A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR. >

Behavioral synthesis for easy testability in data path scheduling

Abstract: A data path scheduling algorithm to improve testability without assuming any particular test strategy is presented. A scheduling heuristic for easy testability, based on previous work on data path allocation for testability, is introduced. A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead. >

The pseudoexhaustive test of sequential circuits

Abstract: The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation. >

A functional fault model for sequential machines

Abstract: A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

A novel approach to delay-fault diagnosis

Abstract: The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

The TInMANN VLSI chip

Abstract: A massively parallel, all-digital, stochastic architecture-TInMANN-that acts as a Kohonen self-organizing feature map is described. A VLSI design is shown for a TInMANN neuron which fits within a small, inexpensive MOSIS TinyChip frame, yet which can be configured to build networks of arbitrary size. The neuron operates at a speed of 15 MHz, making it capable of processing 195000 three-dimensional training examples per second. Three man-months were required to synthesize the neuron and its associated level-sensitive scan logic using the OASIS silicon compiler. The ease of synthesis allowed many performance trade-offs to be examined, while the automatic testability features of the compiler helped the designers achieve 100% fault coverage of the chip. These factors served served to create a fast, dense, and reliable neural chip. >

Equivalence of robust delay-fault and single stuck-fault test generation

Abstract: A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique. >

Dynamic fault tree models: techniques for analysis of advanced fault tolerant computer systems

Abstract: There is a need for the development of methods for evaluating the vulnerability to failure of goods or systems produced using advanced technology. In particular, the systems for which this evaluation is most critical tend to be complex fault tolerant systems intended for applications where a catastrophic failure can mean loss of life. We contribute to this development of evaluation methods by extending the traditionally combinatorial fault tree evaluation method in such a way that it becomes capable of modeling the full range of system behavior that can be expressed with Markov chains for non-repairable systems. The resulting new modeling technique is called dynamic fault trees and combines the best characteristics of both the fault tree and Markov chain modeling methods. This modeling method requires a two-step procedure that is usually needed for analytical modeling methods: model generation followed by model solution. To further extend the dynamic fault tree method, we develop a one-step algorithm in which the model can be solved as it is generated. This helps ease the use of certain approximation methods for reducing model size and helps optimize the use of computation resources.

Behavioral synthesis for easy testability in data path allocation

Abstract: The first behavioral synthesis scheme for improving testability in data path allocation independent of test strategy is presented. The authors propose two behavioral synthesis-for-test heuristics: improve observability and controllability of registers, and reduce sequential depth between registers. Also presented are algorithms that optimize a behavior-level design using these two criteria while minimizing area. Experimental results for benchmark circuits synthesized by the author's experimental system. PHITS, show that these methods give a high fault coverage in small amounts of CPU time at a low area overhead. >

Diagnosis of leakage faults with I DDQ

Abstract: Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.

I DDQ testing in CMOS digital ASICs

Abstract: I DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I DDQ measurement distribution, effects of multiple I DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I DDQ testing was implemented are reviewed. The methods used to establish I DDQ test limits and implement the I DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].

Fault location techniques for radial and loop transmission systems using digital fault recorded data

Abstract: The authors present digital fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals. The systems under consideration are a 115 kV loop transmission system with data available at two terminals and a 69 kV radial transmission system with data available at one terminal. The data under consideration were recorded using digital fault recorders. The conversion of the data to workable data files and the techniques developed to achieve the highest accuracy in determining the fault location are discussed. Intermediate load buses and loads are considered in determining the fault location. An example of the effect of neglecting the presence of these loads is discussed. The fault location techniques are based on both the apparent impedance concept and the use of the three-phase voltage and current phasors. A test case with the exact fault location is presented. The techniques were developed on an IBM PC. >

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Fault injection for the formal testing of fault tolerance

Abstract: The authors address the issue of the use of fault injection for explicitly removing design/implementation faults in fault tolerance algorithms and mechanisms. A formalism is introduced that represents the fault tolerance algorithms and mechanisms by means of a set of assertions. This formalism enables the execution tree to be presented, where each path from the root to a leaf of the tree is a well-defined formula. It provides a framework for the generation of a functional deterministic test for programs implementing complex fault tolerance algorithms and mechanisms. This methodology has been used to extend a debugging tool aimed at testing fault tolerance protocols developed by BULL France. It has been successfully applied to the injection of faults in the inter-replica protocol supporting the application-level fault tolerance features of the architecture of the ESPRIT-funded Delta-4 project. The results of these experiments are discussed and analyzed. >

Advanced fault collapsing (logic circuits testing)

Abstract: The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well. >

Parallel-processing techniques for automatic test pattern generation

Abstract: Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results. >

Behavioral synthesis for easy testability in data path scheduling

Abstract: This paper presents a data path scheduling algorithm to improve testability without a priori assuming any particular test strategy. We introduce a scheduling heuristic for easy testability, based on our previous work [I51 on data path allocation for testability. We then develop a mobility path scheduling algorithm to implement this heuristic while also minimizing area. Experimental results on benchmark and ezample circuits show high fault coverage, short test generation time, and little or no area overhead.

Testability measures in pseudorandom testing

Abstract: The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by multiple fan-out reconvergencies and can be used in testability analysis to predict the fault coverage of pseudorandom patterns. The performances of these algorithms have been tested on significant benchmarks and compare favorably with those of previous procedures. >