Showing papers on "Fault coverage published in 2007"

Fault Detection Using the k-Nearest Neighbor Rule for Semiconductor Manufacturing Processes

Abstract: It has been recognized that effective fault detection techniques can help semiconductor manufacturers reduce scrap, increase equipment uptime, and reduce the usage of test wafers. Traditional univariate statistical process control charts have long been used for fault detection. Recently, multivariate statistical fault detection methods such as principal component analysis (PCA)-based methods have drawn increasing interest in the semiconductor manufacturing industry. However, the unique characteristics of the semiconductor processes, such as nonlinearity in most batch processes, multimodal batch trajectories due to product mix, and process steps with variable durations, have posed some difficulties to the PCA-based methods. To explicitly account for these unique characteristics, a fault detection method using the k-nearest neighbor rule (FD-kNN) is developed in this paper. Because in fault detection faults are usually not identified and characterized beforehand, in this paper the traditional kNN algorithm is adapted such that only normal operation data is needed. Because the developed method makes use of the kNN rule, which is a nonlinear classifier, it naturally handles possible nonlinearity in the data. Also, because the FD-kNN method makes decisions based on small local neighborhoods of similar batches, it is well suited for multimodal cases. Another feature of the proposed FD-kNN method, which is essential for online fault detection, is that the data preprocessing is performed automatically without human intervention. These capabilities of the developed FD-kNN method are demonstrated by simulated illustrative examples as well as an industrial example.

Improving Fault Detection Capability by Selectively Retaining Test Cases during Test Suite Reduction

Abstract: Software testing is a critical part of software development. As new test cases are generated over time due to software modifications, test suite sizes may grow significantly. Because of time and resource constraints for testing, test suite minimization techniques are needed to remove those test cases from a suite that, due to code modifications over time, have become redundant with respect to the coverage of testing requirements for which they were generated. Prior work has shown that test suite minimization with respect to a given testing criterion can significantly diminish the fault detection effectiveness (FDE) of suites. We present a new approach for test suite reduction that attempts to use additional coverage information of test cases to selectively keep some additional test cases in the reduced suites that are redundant with respect to the testing criteria used for suite minimization, with the goal of improving the FDE retention of the reduced suites. We implemented our approach by modifying an existing heuristic for test suite minimization. Our experiments show that our approach can significantly improve the FDE of reduced test suites without severely affecting the extent of suite size reduction

Securing Designs against Scan-Based Side-Channel Attacks

Abstract: Traditionally, the only standard method of testing that has consistently provided high fault coverage has been scan test due to the high controllability and high observability this technique provides. The scan chains used in scan test not only allow test engineers to control and observe a chip, but these properties also allow the scan architecture to be used as a means to breach chip security. In this paper, we propose a technique, called Lock & Key, to neutralize the potential for scan-based side-channel attacks. It is very difficult to implement an all inclusive security strategy, but by knowing the attacker, a suitable strategy can be devised. The Lock & Key technique provides a flexible security strategy to modern designs without significant changes to scan test practices. Using this technique, the scan chains are divided into smaller subchains. With the inclusion of a test security controller, access to subchains are randomized when being accessed by an unauthorized user. Random access reduces repeatability and predictability making reverse engineering more difficult. Without proper authorization, an attacker would need to unveil several layers of security before gaining proper access to the scan chain in order to exploit it. The proposed Lock & Key technique is design independent while maintaining a relatively low area overhead.

Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance

Abstract: Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs, there is substantial interest in adapting such parallel hardware resources for transient fault tolerance. This paper proposes a software-based multi-core alternative for transient fault tolerance using process-level redundancy (PLR). PLR creates a set of redundant processes per application process and systematically compares the processes to guarantee correct execution. Redundancy at the process level allows the operating system to freely schedule the processes across all available hardware resources. PLR's software-centric approach to transient fault tolerance shifts the focus from ensuring correct hardware execution to ensuring correct software execution. As a result, PLR ignores many benign faults that do not propagate to affect program correctness. A real PLR prototype for running single-threaded applications is presented and evaluated for fault coverage and performance. On a 4-way SMP machine, PLR provides improved performance over existing software transient fault tolerance techniques with 16.9% overhead for fault detection on a set of optimized SPEC2000 binaries.

Perturbation-based Fault Screening

Abstract: Fault screeners are a new breed of fault identification technique that can probabilistically detect if a transient fault has affected the state of a processor. We demonstrate that fault screeners function because of two key characteristics. First, we show that much of the intermediate data generated by a program inherently falls within certain consistent bounds. Second, we observe that these bounds are often violated by the introduction of a fault. Thus, fault screeners can identify faults by directly watching for any data inconsistencies arising in an application's behavior. We present an idealized algorithm capable of identifying over 85% of injected faults on the SpecInt suite and over 75% overall. Further, in a realistic implementation on a simulated Pentium-III-like processor, about half of the errors due to injected faults are identified while still in speculative state. Errors detected this early can be eliminated by a pipeline flush. In this paper, we present several hardware-based versions of this screening algorithm and show that flushing the pipeline every time the hardware screener triggers reduces overall performance by less than 1%

A Direct Three-Phase Circuit Analysis-Based Fault Location for Line-to-Line Fault

Abstract: From a direct three-phase circuit analysis, an accurate fault-location algorithm has been obtained for the line-to-line fault as an extension of the author's previous work for line-to-ground fault location. Robustness of the proposed algorithm to load impedance uncertainty is enhanced by the introduction of impedance compensation using voltage and current measurements. Simulation results show a high degree of accuracy and robustness to load uncertainty.

Automatic Instruction-Level Software-Only Recovery

Abstract: Software-only reliability techniques protect against transient faults without the overhead of hardware techniques. Although existing low-level software-only fault-tolerance techniques detect faults, they offer no recovery assistance. This article describes three automatic, instruction-level, software-only recovery techniques representing different trade-offs between reliability and performance

$k$ -out-of- $n$ :G System Reliability With Imperfect Fault Coverage

Abstract: Systems requiring very high levels of reliability, such as aircraft controls or spacecraft, often use redundancy to achieve their requirements. Reliability models for such redundant systems have been widely treated in the literature. These models describe k-out-of-n:G systems, where n is the number of components in the system, and k is the minimum number of components that must work if the overall system is to work. Most of this literature treats the perfect fault coverage case, meaning that the system is perfectly capable of detecting, isolating, and accommodating failures of the redundant elements. However, the probability of accomplishing these tasks, termed fault coverage, is frequently less than unity. Correct modeling of imperfect coverage is critical to the design of highly reliable systems. Even very high values of coverage, only slightly less than unity, will have a major impact on the overall system reliability when compared to the ideal system with perfect coverage. The appropriate coverage modeling approach depends on the system design architecture, particularly the technique(s) used to select among the redundant elements. This paper demonstrates how coverage effects can be computed, using both combinatorial, and recursive techniques, for four different coverage models: perfect fault coverage (PFC), element level coverage (ELC), fault level coverage (FLC), and one-on-one level coverage (OLC). The designation of PFC, ELC, FLC, and OLC to distinguish types of coverage modeling is suggested in this paper.

Minimizing the Impact of Scan Compression

Abstract: Scan is widely accepted as the basis for reducing test cost and improving quality, however its effectiveness is compromised by increasingly complex designs and fault models that can result in high scan data volume and application time. The authors present a scan compression method designed for minimal impact in all aspects: area overhead, timing, and design flow. Easily adopted on top of existing scan designs, the method is fully integrated in the scan synthesis and test generation flows. Data and test time compressions of over 10times were obtained on industrial designs with negligible overhead and no impact on schedule.

Design and Analysis of Reliable and Fault-Tolerant Computer Systems

Abstract: Fundamental Concepts in Fault Tolerance and Reliability Analysis Fault Modeling, Simulation and Diagnosis Error Control and Self-Checking Circuits Fault Tolerance in Multiprocessor Systems Fault-Tolerant Routing in Multi-Computer Networks Fault Tolerance and Reliability in Hierarchical Interconnection Networks Fault Tolerance and Reliability of Computer Networks Fault Tolerance in High Speed Switching Networks Fault Tolerance in Distributed and Mobile Computing Systems Fault Tolerance in Mobile Networks Reliability and Yield Enhancement of VLSI/WSI Circuits Design of fault-tolerant Processor Arrays Algorithm-Based Fault Tolerance System Level Diagnosis I System Level Diagnosis II Fault Tolerance and Reliability of RAID Systems High Availability in Computer Systems.

A BIST TPG for Low Power Dissipation and High Fault Coverage

Abstract: This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

Toward a scalable test methodology for 2D-mesh Network-on-Chips

Abstract: This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.

A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip

Abstract: Network on chips (NoC) have emerged as a feasible solution to handle growing number of communicating components on a single chip. The scalability of chips however increases the probability of errors, hence making reliability a major issue in scaling chips. We hereby propose a comprehensive fault tolerant mechanism for packet based NoCs to deal with packet losses or corruption due to transient faults as well as a dynamic routing mechanism to deal with permanent link and/or router failure on-chip

System and method for rapidly diagnosing bugs of system software

Abstract: A system and a method for rapidly diagnosing bugs of system software are apply for rapidly localizing a system program fault that causes a system error and then feeding back to a subscriber. First, according to the subscriber's requirement, a program of system fault analysis standard is preset and written into the system. Next, a plurality of fault insertion points is added into a program module of the system according to the subscriber's requirement for the precision of the fault analysis result. Then, fault management information is generated at the fault insertion points during the running process of the system program, and the management information is monitored for collecting relevant system fault data. After that, the collected system fault data is analyzed in real time through the program of system fault analysis standard, so as to obtain the minimum fault set for causing the system error.

Test Configurations for Diagnosing Faulty Links in NoC Switches

Abstract: The paper proposes a new concept of diagnosing faulty links in network-on-a-chip (NoC) designs. The method is based on functional fault models and it implements packet address driven test configurations. As previous works have shown, such configurations can be applied for achieving near-100 per cent structural fault coverage for the network switches. The main novel contribution of this paper is to extend the use of test configurations for diagnosis purposes and to propose a method for locating faults in the NoC interconnection infrastructure. Additionally, a new concept of functional switch faults, called link faults, is introduced. The approach is well scalable (complexity is square root of the number of switches) and it is capable of unambiguously pinpointing the faulty links inside the switching network.

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

Abstract: Flash memories are a type of nonvolatile memory based on floating-gate transistors. The use of commodity and embedded flash memories is growing rapidly as we enter the system-on-chip era. Conventional tests for flash memories are usually ad hoc-the test procedure is developed for a specific design. As there is a large number of possible failure modes for flash memories, long test algorithms on complicated automatic test equipment (ATE) are commonly seen. The long test time results in high test cost. We propose a systematic approach in testing flash memories, including the development of March-like test algorithms, cost-effective fault diagnosis methodology, and built-in self-test (BIST) scheme. The improved March-like test algorithms can detect disturb faults-derived from the IEEE STD 1005-and conventional faults. As the memory array architecture and/or cell structure varies, the targeted fault set may change. We have developed a flash-memory fault simulator called RAMSES-FT, with which we can easily analyze and verify the coverage of targeted faults under any given test algorithm. In addition, the RAM test algorithm generator-test algorithm generator by simulation-has been enhanced based on RAMSES-FT, so that one can easily generate tests for flash memories, whether they are bit- or word-oriented. The proposed fault diagnosis methodology helps improve the production yield. We also develop a built-in self-diagnosis (BISD) scheme-a BIST design with diagnosis support. The BISD circuit collects useful test information for off-chip diagnostic analysis. It has unique test mode control that reduces test time and diagnostic data shift-out cycles by a parallel shift-out mechanism

A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture

Abstract: In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any specific clock tree construction, special scan cells, or scan chain reordering. Test cubes generated by any combinational ATPG can be processed by the proposed method to reduce peak and average switching activity without any capture violation. Switching activity during scan shift cycles is reduced by assigning identical values to adjacent scan inputs and switching activity during capture cycles is reduced by limiting the number of scan chains that capture responses. Hardware overhead for the proposed method is negligible. The peak transition is reduced by about 40% and average number of transitions is reduced by about 56-85%. This reduction in peak and average switching activity is achieved with no decrease in fault coverage.

System fault diagnostics using fault tree analysis

Abstract: Over the last 50 years, advances in technology have led to an increase in the complexity and sophistication of systems. More complex systems can be harder to maintain and the root cause of a fault more difficult to isolate. Downtime resultin from a system failure can be dangerous or expensive, depending on the type of system. In aircraft systems the ability to diagnose quickly the causes of a fault can have a significant impact on the time taken to rectify the problem and to return the aircraft to service. In chemical prcess plants the need to diagnose causes of a safety-critical failure in a system can be vital and a diagnosis may be required within minutes. Speed of fault isolation can save time, reduce costs, and increase company productivity and therefore profits. System fault diagnosis is the process of identifying the cause of a malfunction by observing its effect at various test points. Fault tree analysis (FTA) is a method that describes all possible causes of a specified system state in terms of the state of the components within the system. A system model is used to identify the states that the system should be in at any point in time. This paper presents a method for diagnosing faults in systems using FTA to explain the deviations from normal operation observed in sensor outputs. The causes of a system’s failure modes will be described in terms of the component states. This will be achieved with the use of coherent and non-coherent fault trees. A coherent fault tree is constructed from AND and OR logic and therefore considers only component-failed states. The non-coherent method expands this, allowing the use of NOT logic, which implies that the existence of component-failed states and component-working states are both taken into account. This paper illustrates the concepts of this method by applying the technique to a simplified water tank level control system.

Fault Dictionary Based Scan Chain Failure Diagnosis

Abstract: In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.

Toward Reducing Fault Fix Time: Understanding Developer Behavior for the Design of Automated Fault Detection Tools

Abstract: The longer a fault remains in the code from the time it was injected, the more time it will take to fix the fault. Increasingly, automated fault detection (AFD) tools are providing developers with prompt feedback on recently-introduced faults to reduce fault fix time. If however, the frequency and content of this feedback does not match the developer's goals and/or workflow, the developer may ignore the information. We conducted a controlled study with 18 developers to explore what factors are used by developers to decide whether or not to address a fault when notified of the error. The findings of our study lead to several conjectures about the design of AFD tools to effectively notify developers of faults in the coding phase. The AFD tools should present fault information that is relevant to the primary programming task with accurate and precise descriptions. The fault severity and the specific timing of fault notification should be customizable. Finally, the AFD tool must be accurate and reliable to build trust with the developer.

Using model checking to generate fault detecting tests

Abstract: We present a technique which generates from Abstract State Machines specifications a set of test sequences capable to uncover specific fault classes. The notion of test goal is introduced as a state predicate denoting the detection condition for a particular fault. Tests are generated by forcing a model checker to produce counter examples which cover the test goals. We introduce a technique for the evaluation of the fault detection capability of a test set. We report some experimental results which validate the method, compare the fault adequacy criteria with some classical structural coverage criteria and show an empirical cross coverage among faults.

A methodology for detecting performance faults in microprocessors via performance monitoring hardware

Abstract: Speculative execution of instructions boosts performance in modern microprocessors. Control and data flow dependencies are overcome through speculation mechanisms, such as branch prediction or data value prediction. Because of their inherent self-correcting nature, the presence of defects in speculative execution units does not affect their functionality (and escapes traditional functional testing approaches) but impose severe performance degradation. In this paper, we investigate the effects of performance faults in speculative execution units and propose a generic, software-based test methodology, which utilizes available processor resources: hardware performance monitors and processor exceptions, to detect these faults in a systematic way. We demonstrate the methodology on a publicly available fully pipelined RISC processor that has been enhanced with the most common speculative execution unit, the branch prediction unit. Two popular schemes of predictors built around a Branch Target Buffer have been studied and experimental results show significant improvements on both cases fault coverage of the branch prediction units increased from 80% to 97%. Detailed experiments for the application of a functional self-testing methodology on a complete RISC processor incorporating both a full pipeline structure and a branch prediction unit have not been previously given in the literature.

Transient fault detectors

Abstract: We present fault detectors for transient faults, (i.e., corruptions of the memory of the processors, but not of the code of the processors). We distinguish fault detectors for tasks (i.e., the problem to be solved) from failure detectors for implementations (i.e., the algorithm that solves the problem). The aim of our fault detectors is to detect a memory corruption as soon as possible. We study the amount of memory needed by the fault detectors for some specific tasks, and give bounds for each task. The amount of memory is related to the size and the number of views that a processor has to maintain to ensure a quick detection. This work may give the implementation designer hints concerning the techniques and resources that are required for implementing a task.

Built-in self-test of integrated circuits using selectable weighting of test patterns

Abstract: A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.

Improved qualitative fault propagation analysis

Abstract: Fault propagation analysis is the cornerstone to assure safe operation, optimized maintenance, as well as for the management of abnormal situations in chemical and petrochemical plants. Due to plant complexity and dynamic changes in plant conditions, current approaches have major limitations in identifying all possible fault propagation scenarios. This is due to the lack of realistic equipment and fault models. In this paper, practical framework is proposed to synthesize and assess all possible fault propagation scenarios based on robust modeling methodology. Fault models are constructed where deviations are identified and associated with symptoms, faults, causes, and consequences. Fault models are tuned using real time process data, simulation data, and human experience. The proposed system is developed and applied on case study experimental plant.

Fault tree map generation

Abstract: A method for Fault Tree Map generation employs to transformation of Fault Trees of production installation, specific installation, technical system (Hardware and integrated Hardware/Software) to new Fault Tree diagram (Fault Tree Map), which permits drastically compact the Fault Tree depiction and facilitates performing of the Fault Tree qualitative analysis, including evaluation of combination of latent failures and evident failures, repeated events and critical events position influence, and failure propagation potentiality, besides facility of localization of each Fault Tree logical Gate and relevant failures in the fault tree printed report. Generation takes place using special symbols, which permit to reflect the Fault Tree logic, present all Fault Tree failures with graphically identification of the failure type, and show the failure repetition and also the failure critically (importance) to Fault Tree Top Event probability. The method presents exceptional advantages to analysis of large-scale, extended Fault Trees, allowing vastly decrease the time of analysis and elevate the analysis quality and Fault Tree perception, including for specialists, who are not the Fault Tree authors.