Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
Papers published on a yearly basis
Papers
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TL;DR: A synergistic technique framework is proposed that integrates both the ECC and FM techniques to address simultaneously the permanent and transient faults of STT-MRAM, and shows good performance in terms of repair rate and hardware overhead.
Abstract: The emerging spin transfer torque magnetic random access memory (STT-MRAM) promises many attractive features, such as nonvolatile, high speed and low power etc, which enable it to be a promising candidate for the next-generation logic and memory circuits. However with the continuous scaling technology process, the chip yield and reliability of STT-MRAM face severe challenges due to the increasing permanent and transient faults. Due to the intrinsic fault features and the targeted application requirements of STT-MRAM, traditional fault tolerant design solutions, such as error correction code (ECC), redundancy repair (RR), and fault masking (FM) techniques, cannot be employed straightforwardly for STT-MRAM. In this paper, we propose a synergistic technique framework, named sECC, that integrates both the ECC and FM techniques to address simultaneously the permanent and transient faults. With such approach, permanent faults are masked while transient faults are corrected with the same codeword. Moreover taking into consideration the fact that most permanent faults are sparse [about 60%–70% single isolated faults (SIFs)], we propose further integrating the RR and sECC (named iRRsECC) to optimize the system performance. In this scenario, all the SIFs are masked and the transient faults are corrected with the proposed sECC, while other permanent faulty types (e.g., faulty rows or columns) are repaired with redundant rows or columns. A simulation tool is developed to evaluate the proposed techniques and the evaluation results show their good performance in terms of repair rate and hardware overhead.
65 citations
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16 Nov 1999TL;DR: A novel low power/energy built-in self test (BIST) strategy based on circuit partitioning to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage.
Abstract: In this paper, we propose a novel low power/energy built-in self test (BIST) strategy based on circuit partitioning. The goal of the proposed strategy is to minimize the average power, the peak power and the energy consumption during pseudo-random testing without modifying the fault coverage. The strategy consists in partitioning the original circuit into two structural subcircuits so that each subcircuit can be successively tested through two different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. the average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the two subcircuits is roughly the same as the test length for the original circuit. Results on ISCAS circuits show that average power reduction of up to 72%, peak power reduction of up to 53%, and energy reduction of up to 84% can be achieved.
65 citations
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TL;DR: In this article, a theoretical expression is derived that evaluates the effectiveness of a set of logic tests for digital integrated circuits and the validity of the proposed figure of merit is examined with experimental data from CMOS integrated circuits.
Abstract: A theoretical expression is derived in this paper that evaluates the effectiveness of a set of logic tests for digital integrated circuits. The validity of the proposed figure of merit is examined with experimental data from CMOS integrated circuits. In addition, the importance of simulating the nonclassical stuck-open/stuck-on CMOS logic faults is also studied.
65 citations
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TL;DR: An upper bound is found for the minimum number of test patterns required to detect a fault in combinational networks based on Reed-Muller (RM) transforms.
Abstract: A new approach for fault detection in combinational networks based on Reed-Muller (RM) transforms is presented. An upper bound on the number of RM spectral coefficients required to be verified for detection of multiple stuck-at-faults and single bridging faults at the input lines of an n-input network is shown to be n. The time complexity (time required to test a network) for detection of multiple terminal faults and the storage required for storing the test are determined. An upper bound is found for the minimum number of test patterns required to detect a fault. The authors present standard tests based on this result, with a simple test generation procedure and upper bounds on minimal numbers of test patterns. >
65 citations
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05 Sep 2001
TL;DR: In this article, a test coverage tool provides output that identifies differences between the actual coverage provided by a test suite run on a program under test and the coverage criteria required by the test/development team management.
Abstract: A test coverage tool provides output that identifies differences between the actual coverage provided by a test suite run on a program under test and the coverage criteria (e.g., the coverage criteria required by the test/development team management). The output from the test coverage tool is generated in the same language that was used to write the coverage criteria that are input to an automated test generator to create the test cases which form the test suite. As a result, the output from the coverage tool can be input back into the automated test generator to cause the generator to revise the test cases to correct the inadequacies. This allows iterative refinement of the test suite automatically, enabling automated test generation to be more effectively and efficiently used with more complex software and more complex test generation inputs. In preferred embodiments, test coverage analysis results of several different test suites, some manually generated and others automatically generated, are used to produce a streamlined automatically-generated test suite and/or to add missing elements to an automatically generated test-suite.
65 citations