Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Fault equivalence and diagnostic test generation using ATPG

Abstract: Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. This is performed with a simple hardware construction and a sequence of simulation/ATPG-based steps. Experiments on benchmark circuits demonstrate the competitiveness of the proposed method.

Defect-oriented testing and defective-part-level prediction

Abstract: After an integrated circuit (IC) design is complete, but before first silicon arrives from the manufacturing facility, the design team prepares a set of test patterns to isolate defective parts. Applying this test pattern set to every manufactured part reduces the fraction of defective parts erroneously sold to customers as defect-free parts. This fraction is referred to as the defect level (DL). However, many IC manufacturers quote defective part level, which is obtained by multiplying the defect level by one million to give the number of defective parts per million. Ideally, we could accurately estimate the defective part level by analyzing the circuit structure, the applied test-pattern set, and the manufacturing yield. If the expected defective part level exceeded some specified value, then either the test pattern set or (in extreme cases) the design could be modified to achieve adequate quality. Although the IC industry widely accepts stuck-at fault detection as a key test-quality figure of merit, it is nevertheless necessary to detect other defect types seen in real manufacturing environments. A defective-part-level model combined with a method for choosing test patterns that use site observation can predict defect levels in submicron ICs more accurately than simple stuck-at fault analysis.

A comparison of bridging fault simulation methods

Abstract: This study provides bridging fault simulation data obtained from the AMD-K6 microprocessor. It shows that: (1) high stuck-at fault coverage (99.5%) implies high bridging fault coverage; (2) coverage of a bridging fault by both wired-AND and wired-OR behavior does not guarantee detection of that fault when compared against a more accurate (transistor-level simulation) modeling method. A set of netname pairs representing bridging fault sites were extracted from layout and used for each fault modeling method. Results show that pattern generation should be driven by the most accurate modeling method when pursuing 100% bridging coverage, since less accurate methods will not necessarily converge to a high quality result.

One-terminal fault location system that corrects for fault resistance effects

Abstract: A one-terminal process for locating a fault associated with a multi-phase electric power transmission system is disclosed. The process is based on the principle that the impedance in a fault can be determined by correcting errors due to the interaction of fault resistance and load current. The fault may be a phase-to-ground fault or a multiple-phase fault.

Using BIST control for pattern generation

Abstract: A deterministic BIST scheme is presented which requires less hardware overhead than pseudo-random BIST but obtains better or even complete fault coverage at the same time. It takes advantage of the fact that any autonomous BIST scheme needs a BIST control unit for indicating the completion of the self-test at least. Hence, pattern counters and bit counters are always available, and they provide information to be used for deterministic pattern generation by some additional circuitry. This paper presents a systematic way for synthesizing a pattern generator which needs less area than a 32-bit LFSR for random pattern generation for all the benchmark circuits.