Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Design techniques and test methodology for low-power TCAMs

Abstract: Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage

How To Do Weighted Random Testing For Bist

Abstract: In this paper, a strategy as proposed whach takes into account all aspects of wezghted random testzng for BIST. Our approach arwes from results concernzng the ampact of wezght roundang and a new combznataon of known technzques lake couplzng unweaghted and weighted pattern generatzon, basang weaght calculatzon on a precomputed test [2, 61, numerical maxzmazataon of pattern coverage [4], GURT-like hardware amplementatzon [lo], and avozdzng auto-correlataons. As an empiracal evaluation, we examzned the only random pattern resastant ISCAS 85 benchmarks c2670 and c7552. For these ctrcuats, 100% fault coverage was achieved after a total of 16,000 and 256,000 patterns, respectively. The hardware overhead compared to a pure random test as less than 2.5%.

Behavioral synthesis for easy testability in data path scheduling

Abstract: A data path scheduling algorithm to improve testability without assuming any particular test strategy is presented. A scheduling heuristic for easy testability, based on previous work on data path allocation for testability, is introduced. A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed. Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead. >

The pseudoexhaustive test of sequential circuits

Abstract: The concept of a pseudoexhaustive test for sequential circuits is introduced in a way similar to that which is used for combinational networks. Using partial scan all cycles in the data flow of a sequential circuit are removed, such that a compact combinational model can be constructed. Pseudoexhaustive test sequences for the original circuit are constructed from a pseudoexhaustive test set for this model. To make this concept feasible for arbitrary circuits a technique for circuit segmentation is presented which provides special segmentation cells as well as the corresponding algorithms for the automatic placement of the cells. Example circuits show that the test strategy requires less additional silicon area than a complete scan path. Thus the advantages of a partial scan path are combined with the well-known benefits of a pseudoexhaustive test, such as high fault coverage and simplified test generation. >