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Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.


Papers
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Journal ArticleDOI
TL;DR: The efficacy of the proposed approach is illustrated with data acquired from bearings typically found on aircraft and monitored via a properly instrumented test rig, and the scheme provides the probability of abnormal condition and the presence of a fault is confirmed for a given confidence level.
Abstract: This paper introduces a method to detect a fault associated with critical components/subsystems of an engineered system. It is required, in this case, to detect the fault condition as early as possible, with specified degree of confidence and a prescribed false alarm rate. Innovative features of the enabling technologies include a Bayesian estimation algorithm called particle filtering, which employs features or condition indicators derived from sensor data in combination with simple models of the system's degrading state to detect a deviation or discrepancy between a baseline (no-fault) distribution and its current counterpart. The scheme requires a fault progression model describing the degrading state of the system in the operation. A generic model based on fatigue analysis is provided and its parameters adaptation is discussed in detail. The scheme provides the probability of abnormal condition and the presence of a fault is confirmed for a given confidence level. The efficacy of the proposed approach is illustrated with data acquired from bearings typically found on aircraft and monitored via a properly instrumented test rig.

246 citations

Proceedings ArticleDOI
03 Nov 2003
TL;DR: Experimental results show that the proposed approach is far more effective than the other considered techniques in terms of fault detection capability, at the cost of a limited increase in memory requirements and in performance overhead.
Abstract: Over the last few years, an increasing number of safety-critical tasks have been demanded of computer systems. In this paper, a software-based approach for developing safety-critical applications is analyzed. The technique is based on the introduction of additional executable assertions to check the correct execution of the program control flow. By applying the proposed technique, several benchmark applications have been hardened against transient errors. Fault injection campaigns have been performed to evaluate the fault detection capability of the proposed technique in comparison with state-of-the-art alternative assertion-based methods. Experimental results show that the proposed approach is far more effective than the other considered techniques in terms of fault detection capability, at the cost of a limited increase in memory requirements and in performance overhead.

244 citations

Journal ArticleDOI
R. Dekker1, F. Beenker1, L. Thijssen
TL;DR: A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented and two linear test algorithms that cover 100% of the faults under the fault model are proposed.
Abstract: Testing static random access memories (SRAMs) for all possible failures is not feasible and one must restrict the class of faults to be considered. This restricted class is called a fault model. A fault model for SRAMs based on physical spot defects, which are modeled as local disturbances in the layout of the SRAM, is presented. Two linear test algorithms that cover 100% of the faults under the fault model are proposed. A general solution is given for testing word-oriented SRAMs. The practical validity of the fault model and the two test algorithms are verified by a large number of actual wafer tests and device failure analyses. >

242 citations

Journal ArticleDOI
01 Nov 1990
TL;DR: In this article, the authors describe a very accurate fault location technique which uses post-fault voltage and current derived at both line ends, independent of fault resistance and the method does not require any knowledge of source impedance.
Abstract: The authors describe a very accurate fault location technique which uses post-fault voltage and current derived at both line ends. Fault location is independent of fault resistance and the method does not require any knowledge of source impedance. It maintains high accuracy for untransposed lines and no fault type identification is required. The authors present the theory of the technique and the results of simulation studies to determine its performance.< >

239 citations

Proceedings ArticleDOI
26 Oct 1991
TL;DR: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed and can be added to existing test pattern generators without compromising fault coverage.
Abstract: Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics. >

237 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202360
2022135
202167
202089
2019120
2018151