Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

System and method for autonomously processing faults in home network environments

Abstract: There are provided a fault processing system and method for quickly and accurately diagnosing a fault and autonomously processing the fault, based on interdependencies between various devices, networks, systems, and services in home network environments, the method including: establishing fault detection rules for detecting faults belonging to respective fault types defined for each situation by classifying faults occurring in the home network environments, fault diagnosis rules for diagnosing a fault type of a fault, and fault processing rules defining a method of solving a fault for each fault type; collecting state information of devices, networks, services, and the system in the home network environments and detecting a fault based on the fault detection rules; diagnosing the fault type of the detected fault by applying the fault diagnosis rules; and processing the detected fault based on the fault processing rules according to the diagnosed fault type.

Concurrent fault simulation for logic designs

Abstract: A system for concurrent evaluation of the effect of multiple faults in a logic design being evaluated is particularly useful in the design of very large scale integrated circuits for developing a compact input test set which will permit locating a predetermined percentage of all theoretically possible fault conditions in the manufactured chips. The system includes logic evaluation hardware for simulating a given logic design and evaluating the complete operation thereof prior to committing the design to chip fabrication. In addition, and concurrently with the logic design evaluation, the system includes means for storing large number of predetermined fault conditions for each gate in the design, and for evaluating the "fault operation" for each fault condition for each gate, and comparing the corresponding results against the "good machine" operation, and storing the fault operation if different from the good operation. By repeating the process on an event-driven basis from gate to subsequently affected gates throughout the design, a file of all fault effects can be developed from which an input test set for the logic design can be developed based on considerations of the required percentage of all possible faults to be detected and the time that can be allowed for testing of each chip. Special hardware is provided for identifying and eliminating hyperactive or oscillating faults to maintain processing efficiency.

Flexible Synchronized Measurement Technology-Based Fault Locator

Abstract: This paper presents a flexible and robust numerical algorithm for fault location on transmission lines. The algorithm does not require line parameters to locate the fault, which is an advance over fault locators that do require such information. Line parameters are only approximately constant; they vary with different loading and weather conditions, which affects the accuracy of existing fault location algorithms. Thus, an approach which does not require line parameters would be more robust, accurate, and flexible. Accurately, locating faults on transmission lines is vital for expediting their repair, so the proposed solution could lead to an improvement in the security and quality of the energy supply. Development of the proposed algorithm was facilitated by new smart grid technologies in the field of wide-area monitoring, protection, and control. The proposed algorithm is based on emerging synchronized measurement technology, using synchronized data sampling at both line terminals; however, the “SynchroCheck” procedure is also proposed as a means of accurately locating faults when data sampling synchronization has been lost. This paper presents the algorithm derivation and the results of thorough testing using alternative transients program-electromagnetic transients program (ATP-EMTP) fault simulations.

Equivalence of robust delay-fault and single stuck-fault test generation

Abstract: A link between the problems of robust delay-fault and single stuck-fault test generation is established. In particular, it is proved that all the robust test vector pairs for any path delay-fault in a network are directly obtained by all the test vectors for a corresponding single stuck-fault in a modified network. Since single stuck-fault test generation is a well solved problem, this result yields an efficient algorithm for robust delay-fault test generation. Experimental results demonstrate the efficiency of the proposed technique. >