Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Launch-on-Shift-Capture Transition Tests

Abstract: The two most popular transition tests are launch-on-shift (LOS) test and launch-on-capture (LOC) test. The LOS and LOC tests differ in their launch mechanisms, creating their own pros and cons. In this paper, new hybrids of LOS and LOC tests that launch transitions using both launch mechanisms are introduced. The new transition tests improved fault coverage without significant test length penalty. This paper presents the concepts and pattern generation methods of these new transition tests as well as experimental results that demonstrate the benefits of these tests.

Non-Scan Design-for-Testability Techniques for Sequential Circuits

Abstract: Recent studies show that a stuck-at test applied at the operational speed of the circuit identifies more defective chips than a test having the same fault coverage but applied at a lower speed. In this work, we investigate various design-for-testability (DFT) techniques for sequential circuits which permit at-speed application of tests while providing for very high fault coverage. The method involves parallel loading of flip-flops in test mode for enhanced controllability combined with probe point insertion for enhanced observability. Selection of candidate flip-flops and probe points is determined automatically by our OPUS-NS tool. Fault coverage and ATG effectiveness improved to greater than 96% and 99.7%, respectively, for the ISCAS89 sequential benchmark circuits studied when these non-scan DFT techniques were used.

Transmission Line Fault Detection & Phase Selection using ANN

Abstract: A novel application of neural network approach to protection of transmission line is demonstrated in this paper Different system faults on a protected transmission line should be detected and classified rapidly and correctly This paper presents the use of neural networks as a protective relaying pattern classifier algorithm The proposed method uses current signals to learn the hidden relationship in the input patterns Using the proposed approach, fault detection, classification and faulted phase selection could be achieved within a quarter of cycle An improved performance is experienced once the neural network is trained sufficiently and suitably, thus performing correctly when faced with different system parameters and conditions Results of performance studies show that the proposed neural network- based module can improve the performance of conventional fault selection algorithms In this paper, a new scheme is proposed for fast and reliable fault detection and phase selection The proposed method uses an artificial neural network-based scheme Various transient system faults are modeled and an ANN- based algorithm is used for recognition of these patterns Performance of the proposed scheme is evaluated using various fault types and encouraging results are obtained It is shown that the algorithm is able to perform fast and correctly for different combinations of fault conditions, eg fault type, fault resistance, fault inception angle, fault location, prefault power flow direction and system short circuit level

Deterministic software-based self-testing of embedded processor cores

Abstract: A deterministic software-based self-testing methodology for processor cores is introduced that efficiently tests the processor datapath modules without any modification of the processor structure. It provides a guaranteed high fault coverage without repetitive fault simulation experiments which is necessary in pseudorandom software-based processor self-testing approaches. Test generation and output analysis are performed by utilizing the processor functional modules like accumulators (arithmetic part of ALU) and shifters (if they exist) through processor instructions. No extra hardware is required and there is no performance degradation.