Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Increased CMOS IC stuck-at fault coverage with reduced I/sub DDQ/ test sets

Abstract: The authors discuss the significant improvements that were achieved when a conventional ATPG (automatic test pattern generation) algorithm was modified to generate test sets suitable for I/sub DDQ/ testing. These improvements include increased SAF (stuck-at-fault) coverage, reduced vector set sizes, coverage of logically redundant SAFs and multiple SAFs, increased coverage of CMOS IC non-SAF defects, and reduced CPU cost for ATPG and fault simulation. This reduction in computational complexity for I/sub DDQ /based ATPG enables test generation for much larger circuits than previously possible. Additionally untestable faults can be further categorized to identify SAFs that are truly 'don't-care faults,' thereby offering a more realistic assessment of actual fault coverage. >

Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments

Abstract: The probability of transient faults increases with the evolution of technologies. There is a corresponding increased demand for an early analysis of erroneous behaviours. This paper discusses alternative approaches to perform transient fault injection in circuits described in a high level language such as VHDL. In the proposed analysis flow, a behavioural model is generated, allowing the designer to identify the detailed error propagation paths in the circuit. This paper also reports on results obtained with SEU-like fault injections in VHDL descriptions of digital circuits. Several circuit description levels are considered, as well as several fault modelling levels. These results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs.

A BIST TPG for Low Power Dissipation and High Fault Coverage

Abstract: This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST. Test patterns generated by the LT-RTPG detect easy-to-detect faults and test patterns generated by the 3-weight WRBIST detect faults that remain undetected after LT-RTPG patterns are applied. The proposed BIST TPG does not require modification of mission logics, which can lead to performance degradation. Experimental results for ISCAS'89 benchmark circuits demonstrate that the proposed BIST can significantly reduce switching activity during BIST while achieving 100% fault coverage for all ISCAS'89 benchmark circuits. Larger reduction in switching activity is achieved in large circuits. Experimental results also show that the proposed BIST can be implemented with low area overhead.

Automatic Synthesis of Static Fault Trees from System Models

Abstract: Fault tree analysis (FTA) is a traditional reliability analysis technique. In practice, the manual development of fault trees could be costly and error-prone, especially in the case of fault tolerant systems due to the inherent complexities such as various dependencies and interactions among components. Some dynamic fault tree gates, such as Functional Dependency (FDEP) and Priority AND (PAND), are proposed to model the functional and sequential dependencies, respectively. Unfortunately, the potential semantic troubles and limitations of these gates have not been well studied before. In this paper, we describe a framework to automatically generate static fault trees from system models specified with SysML. A reliability configuration model (RCM) and a static fault tree model (SFTM) are proposed to embed system configuration information needed for reliability analysis and error mechanism for fault tree generation, respectively. In the SFTM, the static representations of functional and sequential dependencies with standard Boolean AND and OR gates are proposed, which can avoid the problems of the dynamic FDEP and PAND gates and can reduce the cost of analysis based on a combinatorial model. A fault-tolerant parallel processor (FTTP) example is used to demonstrate our approach.