Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Simulation-based test algorithm generation for random access memories

Abstract: Although there are well known test algorithms that have been used by the industry for years for testing semiconductor random-access memories (RAMs), systematic evaluation of their effectiveness and efficiency has been a difficult job. In the past, it was mainly done manually by proving a certain algorithm can detect a certain type of fault. As memory technology keeps innovating, the growing complexity of the memories and number of fault types that need to be covered will require more effective and efficient test algorithms to be discovered in much shorter time. A systematic approach for developing and evaluating memory test algorithms is thus desired. We propose such an approach here: test algorithm generation by simulation (TAGS), which generates and optimizes test algorithms, given a test time budget. Experimental results show that the algorithms generated by TAGS are more efficient than the traditional test algorithms. Using TAGS, a series of test algorithms with a detailed list of faults covered by each algorithm can be generated, providing easy trade-off between test time and fault coverage.

Built-In Self-Test of Logic Blocks in FPGAs

Abstract: We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcolme these limitations.’

At-speed on-chip diagnosis of board-level interconnect faults

Abstract: This article describes a novel approach to fault diagnosis suitable for at-speed testing of board-level interconnect faults.This approach is based on a new parallel test pattern generator and a specifically fault detecting sequence. The test sequence has tree major advantages.At first, it detects both static and dynamic faults upon interconnects. Secondly, it allows precise on-chp at-speed fault diagnosis of interconnect faults.Third, the hardware implementation of both the test generator and the response analyzer is very efficient in terms of silicon area.

Transmission line fault location for double phase-to-earth fault on non-direct-ground neutral system

Abstract: An accurate algorithm for locating double phase-to-earth faults on transmission lines of nondirect ground neutral systems is presented. The algorithm employs the faulted phase network and zero-sequence network as the fault location model. It effectively eliminates the effect of load flow and fault resistance on the accuracy of fault location. The technique embodies an accurate location by measuring only one local end data. The algorithm is used in a procedure that provides the automatic determination of faulted line and phase, rather than requires engineer to specify them. Simulation results have shown the effectiveness of the algorithm under the condition of earth faults.