Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

I DDQ testing in CMOS digital ASICs

Abstract: I DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I DDQ measurement distribution, effects of multiple I DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I DDQ testing was implemented are reviewed. The methods used to establish I DDQ test limits and implement the I DDQ test with existing ATG testing are included. This article is a revision of one given at International Test Conference [1].

A novel concurrent error detection scheme for FFT networks

Abstract: The algorithm-based fault tolerance techniques have been proposed to obtain reliable results at very low hardware overhead. Even though 100% fault coverage can be theoretically obtained by using these techniques, the system performance, i.e., fault coverage and throughput, can be drastically reduced due to many practical problems, e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed for fast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves 100% fault coverage theoretically. An accurate measure of the fault coverage for FFT networks is provided by taking the round-off error into account. The proposed scheme is shown to provide concurrent error detection capability to FFT networks with low hardware overhead, high throughput, and high fault coverage. >

SOPRANO: an efficient automatic test pattern generator for stuck-open faults in CMOS combinational circuits

Abstract: In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.

Test point insertion for compact test sets

Abstract: Efficient production testing is frequently hampered because (cores in) current complex digital circuit designs require too large test sets, even with powerful ATPG tools that generate compact test sets. Built-in Self-Test approaches often suffer from fault coverage problems, due to random-resistant faults, which can be improved successfully by means of Test Point Insertion (TPI). In this paper, we evaluate the effect of TPI for BIST on the compactness of ATPG generated test sets and it turns out that most often a significant test set size reduction can be obtained. We also propose a novel TPI method, specifically aimed at facilitating compact test generation, based on the ''test counting' technique. Experimental results indicate that the proposed method results in even larger and moreover more consistent reduction of test set sizes.

Fault location techniques for radial and loop transmission systems using digital fault recorded data

Abstract: The authors present digital fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals. The systems under consideration are a 115 kV loop transmission system with data available at two terminals and a 69 kV radial transmission system with data available at one terminal. The data under consideration were recorded using digital fault recorders. The conversion of the data to workable data files and the techniques developed to achieve the highest accuracy in determining the fault location are discussed. Intermediate load buses and loads are considered in determining the fault location. An example of the effect of neglecting the presence of these loads is discussed. The fault location techniques are based on both the apparent impedance concept and the use of the three-phase voltage and current phasors. A test case with the exact fault location is presented. The techniques were developed on an IBM PC. >