Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Multiple fault diagnosis using n-detection tests

Abstract: We study the relationship between multiple fault diagnosability and fault detection count. Instead of developing a complex diagnostic algorithm for multiple fault behavior, we change the test sets used in test and diagnosis. This allows us to apply a simple single-fault based diagnostic algorithm, and yet achieve very good diagnosability for the failure test cases caused by multiple faults. We have verified experimentally the effectiveness of n-detection tests for multiple-fault cases and explained the results in probabilistic terms.

An automated fault diagnosis system using hierarchical reasoning and alarm correlation

Abstract: A slight fault may even cause critical disruptions or remediless damages to the network while a network manager is lost in a large number of alarms. Therefore, the development of a practical and effective system for network fault diagnosis becomes an urgent job. We develop a hierarchical domain-oriented reasoning mechanism suitable for the delegated management architecture. It is based on the causality graph of the sensibly-reduced network fault propagation model from the result of our empirical study. An automated fault diagnosis system called ACView (Alarm Correlation View) for isolating network faults in a multidomain environment is proposed according to the hierarchical reasoning mechanism. This diagnosis system provides not only the process of automated alarm collection and correlation, but also the function of efficient fault localization and identification.

Benefits of vertically stacked integrated circuits for sequential logic

Abstract: Future demands for performance of electronic systems will push the development of three-dimensional (3-D) packaging technologies. Up to now 3-D stacking techniques are just used to realize high density memory modules. In this paper we investigate problems and solutions of sequential logic circuit design for vertically stacked integrated circuits (VIC). We analyze a test strategy and a 3-D placement tool for VICs that allows us to generate globally optimized circuit layouts by a 3-D arrangement of gates. Our focus is on test overhead obtained by the proposed test strategy for VICs and the reduction of wiring space attained by 3-D routing. Additionally we discuss the effect of our 3-D placement procedure on fault coverage. The results obtained using this procedure in different circuit layouts for 3-D circuits are compared to single chip solutions.

A novel differential scan attack on advanced DFT structures

Abstract: Scan chains insertion is the most common technique to ensure the testability of digital cores, providing high fault coverage. However, for ICs dealing with secret information, scan chains can be used as back doors for accessing secret data thus becoming a threat to system security. So far, advanced test structures used to reduce test costs (e.g., response compaction) and achieve high fault coverage (e.g., X's masking decoder) have been considered as intrinsic countermeasures against these threats. This work proposes a new generic scan-based attack demonstrating that these test structures are not sufficiently effective to prevent leakage through the test infrastructure. This generic attack can be easily adapted to several cryptographic implementations for both symmetric and public key algorithms. The proposed attack is demonstrated on several ciphers.