Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Genetic Algorithm-based Test Generation for Software Product Line with the Integration of Fault Localization Techniques

Abstract: In response to the highly competitive market and the pressure to cost-effectively release good-quality software, companies have adopted the concept of software product line to reduce development cost. However, testing and debugging of each product, even from the same family, is still done independently. This can be very expensive. To solve this problem, we need to explore how test cases generated for one product can be used for another product. We propose a genetic algorithm-based framework which integrates software fault localization techniques and focuses on reusing test specifications and input values whenever feasible. Case studies using four software product lines and eight fault localization techniques were conducted to demonstrate the effectiveness of our framework. Discussions on factors that may affect the effectiveness of the proposed framework is also presented. Our results indicate that test cases generated in such a way can be easily reused (with appropriate conversion) between different products of the same family and help reduce the overall testing and debugging cost.

Evaluating the performance of fault detection and diagnostics protocols applied to air-cooled unitary air-conditioning equipment

Abstract: Fault detection and diagnostics tools are increasingly being applied to air-cooled unitary air-conditioning systems. However, it is not known how well these tools work because there is no standard method of measuring or evaluating the performance of fault detection and diagnostics. This article describes the common faults to which fault detection and diagnostics is applied in unitary systems and proposes a method of evaluating the performance of fault detection and diagnostics protocols. The method involves feeding measurement data through a candidate protocol and collecting and organizing the responses based upon the fault's impacts on performance. A library of faulted and unfaulted measurement data has been built and is described. Standard definitions are proposed for several pertinent terms and quantities. A case study is used to demonstrate the evaluation method, using a publicly available fault detection and diagnostics protocol that is evaluated using the complete library of data. This protocol is f...

Improved SAT-based ATPG: more constraints, better compaction

Abstract: Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT) is a robust alternative to classical structural ATPG. Due to the powerful reasoning engines of modern SAT solvers, SAT-based algorithms typically provide a high test coverage because of the ability to reliably classify hard-to-detect faults. However, a drawback of SAT-based ATPG is the test compaction ability. In this paper, we propose an enhanced dynamic test compaction approach which leverages the high implicative power of modern SAT solvers. Fault detection constraints are encoded into the SAT instance and a formal optimization procedure is applied to increase the detection ability of the generated tests. Experiments show that the proposed approach is able to achieve high compaction -- for certain benchmarks even smaller test sets than the currently best known results are obtained.

Seed encoding with LFSRs and cellular automata

Abstract: Reseeding is used to improve fault coverage of pseudo-random testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present a technique for encoding a given seed by the number of clock cycles that the PRPG needs to run to reach it. This encoding requires many fewer bits than the bits of the seed itself. The cost is the time to reach the intended seed. We reduce this cost using the degrees of freedom (due to don't cares in test patterns) in solving the equations for the seeds. We show results for implementing our technique completely in on-chip hardware and for applying it from a tester. Simulations show that with low hardware overhead, the technique provides 100% single-stuck fault coverage. Also, when compared with conventional reseeding from an external tester or on-chip ROM, the technique reduces seed storage by up to 85%. We show how to apply the technique for both LFSRs and CA.

Partial scan by use of empirical testability

Abstract: The objective of the partial scan method proposed is to obtain maximum fault coverage for the number of scan elements selected. Empirical testability difference (ETD), a measure of the potential improvement in the overall testability of the circuit, is used to successively select storage elements for scan. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the actual test sequence generator. In addition, ETD focuses on the hard-to-detect faults rather than all faults once such faults are known. The method has been extensively tested with ten of the sequential circuits given by F. Brglez et al. (1989) using the FASTEST provided by T. Kelsey and K. Saluja (1989). The results of these tests indicate that ETD yields on average either 27% of the number of uncovered faults for the same number of scan elements or 21% fewer scan elements for the same fault coverage compared to the other methods studied. >