Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

On the fault coverage of gate delay fault detecting tests

Abstract: This paper addresses the problem of obtaining accurate fault coverages for the gate delay fault model. For a gate delay fault, it is not sufficient to only find a test. One also has to accurately determine the size of the fault detected. We first show that previous methodologies for determining gate delay fault coverages have certain limitations. A method is then investigated to determine all the possible ranges of detected fault sizes, using the traditional fixed sampling time approach. However, with the constraints of a realistic inertial delay model, it is then shown that it might still not be possible to achieve the coverages required to guarantee circuit operation without malfunctions. A new and more realistic delay model is proposed to obtain true fault coverages that extend up to the actual circuit slacks whenever possible. An alternate test application strategy, involving the usage of varying sampling times, is also proposed to further enhance the actual fault coverages obtained under the proposed delay model. Results of experiments performed to evaluate these methods are given.

Test design optimizer for configurable scan architectures

Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

Test cost minimization through adaptive test development

Abstract: The ever-increasing complexity of mixed-signal circuits imposes an increasingly complicated and comprehensive parametric test requirement, resulting in a highly lengthened manufacturing test phase. Attaining parametric test cost reduction with no test quality degradation constitutes a critical challenge during test development. The capability of parametric test data to capture systematic process variations engenders a highly accurate prediction of the efficiency of each test for a particular lot of chips even on the basis of a small quantity of characterized data. The predicted test efficiency further enables the adjustment of the test set and test order, leading to an early detection of faults. We explore such an adaptive strategy, by introducing a technique that prunes the test set based on a test correlation analysis. A test selection algorithm is proposed to identify the minimum set of tests that delivers a satisfactory defect coverage. A probabilistic measure that reflects the defect detection efficiency is used to order the test set so as to enhance the probability of an early detection of faulty chips. The test sequence is further optimized during the testing process by dynamically adjusting the initial test order to adapt to the local defect pattern fluctuations in the lot of chips under test. Experimental results show that the proposed technique delivers significant test time reductions while attaining higher test quality compared to previous adaptive test methodologies.

VLSI design synthesis with testability

Abstract: A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary tree data structure is used throughout the testable design search. Its bottom up and top down tree algorithms provide datapath allocation, constraint estimation, and feedback for design exploration. The partitioning and two dimensional characteristics of the binary tree structure provide VLSI design floorplans and global information for test incorporation. An elliptical wave filter example was used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple chain scan paths and BIST with different test schedules were explored. Design Scores comprised of area, delay, fault coverage, and test length were computed and graphed. Results show that the 'best' testable design solution is not always the same as that obtained from the 'best' design solution of an area and delay based synthesis search.