Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
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11 Sep 2010
TL;DR: DAFT is presented, a fast, safe, and memory efficient transient fault detection framework for commodity multicore systems that replicates computation across multiple cores and schedules fault detection off the critical path.
Abstract: Higher transistor counts, lower voltage levels, and reduced noise margin increase the susceptibility of multicore processors to transient faults. Redundant hardware modules can detect such errors, but software transient fault detection techniques are more appealing for their low cost and flexibility. Recent software proposals double register pressure or memory usage, or are too slow in the absence of hardware extensions, preventing widespread acceptance. This paper presents DAFT, a fast, safe, and memory efficient transient fault detection framework for commodity multicore systems. DAFT replicates computation across multiple cores and schedules fault detection off the critical path. Where possible, values are speculated to be correct and only communicated to the redundant thread at essential program points. DAFT is implemented in the LLVM compiler framework and evaluated using SPEC CPU2000 and SPEC CPU2006 benchmarks on a commodity multicore system. Results demonstrate DAFT's high performance and broad fault coverage. Speculation allows DAFT to reduce the perfor- mance overhead of software redundant multithreading from an average of 200% to 38% with no degradation of fault coverage.
45 citations
TL;DR: Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed and several techniques that have been used to parallelize ATPG are presented.
Abstract: Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results. >
45 citations
01 Jun 1991
TL;DR: The single transition fault model is augmented by carefully selected multiple transition faults which potentially increase the coverage of single stuck-at faults and experimental results for stuck- at faults are presented.
Abstract: A complete method is presented for generating tests for sequential machines. The transition fault model is employed, and the machine is assumed to be described by a state table. The test generation algorithm described is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given transition fault, the algorithm provides either a test, or a proof that the fault is undetectable. The relationship between transition faults and stuck-at faults is investigated. The single transition fault model is augmented by carefully selected multiple transition faults which potentially increase the coverage of single stuck-at faults. A method to achieve 100% fault efficiency for stuck-at faults is then proposed, and experimental results for stuck-at faults are presented.
45 citations
08 Nov 1992
TL;DR: A mobility path scheduling algorithm to implement this heuristic while also minimizing area is developed and Experimental results on benchmark and example circuits show high fault coverage, short test generation time, and little or no area overhead.
Abstract: This paper presents a data path scheduling algorithm to improve testability without a priori assuming any particular test strategy. We introduce a scheduling heuristic for easy testability, based on our previous work [I51 on data path allocation for testability. We then develop a mobility path scheduling algorithm to implement this heuristic while also minimizing area. Experimental results on benchmark and ezample circuits show high fault coverage, short test generation time, and little or no area overhead.
45 citations
01 Jul 1993
TL;DR: This paper presents a new method for selecting flip-flops for partial scan based on a sensitivity analysis that determines the improvement in the testability of the circuit as a result of scanning a flip- flop.
Abstract: In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops based on a sensitivity analysis that determines the improvement in the testability of the circuit as a result of scanning a flip-flop. Testability is computed with respect to a given set of target faults. Our method can estimate the number of scan flip-flops needed to reach a good fault coverage.
45 citations