Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Accuracy improvement of impedance-based fault location method for power distribution network using distributed-parameter line model

Abstract: SUMMARY Power Distribution System (PDS) is spread on different places. Therefore, PDS has many laterals and load taps. Accurate fault locating in PDS causes to improve reliability indices and its efficiency. In this paper, an improved method is suggested for fault location in PDS, which has a high accuracy. In the proposed algorithm, by using phase domain of distributed-parameter line model, a fifth-order algebraic equation of fault distance is obtained, which can improve the accuracy of determined fault distance for all types of faults. The proposed method is tested under different fault resistances in which the results show low sensitivity to this parameter. To evaluate the accuracy of the proposed method, the modified IEEE 34 Node Test Feeder is used, and its efficiency and accuracy is proved. Copyright © 2012 John Wiley & Sons, Ltd.

Defect Aware Test Patterns

Abstract: A method to generate test patterns referred to as defect aware test patterns is proposed. Defect aware test patterns have greater ability to detect un-modeled defects. The proposed method can be used with any test generation procedure to improve the effectiveness of the tests in detecting un-modeled defects. Experimental results on several industrial designs show the effectiveness of defect aware tests. We also propose a measure to estimate the effectiveness of given test sets in detecting un-modeled defects.

A technique for automated validation of fault tolerant designs using laser fault injection (LFI)

Abstract: This paper describes the successful development and demonstration of a Laser Fault Injection (LFI) technique to inject soft, i.e., transient, faults into VLSI circuits in a precisely-controlled, non-destructive, non-intrusive manner for the purpose of validating fault tolerant design and performance. The technique described in this paper not only enables the validation of fault-tolerant VLSI designs, but it also offers the potential for performing automated testing of board-level and system-level fault tolerant designs including fault tolerant operating system and application software. The paper describes the results of LFI testing performed to date on test metal circuit structures, i.e., ring oscillators, flip-flops, and multiplier chains, and on an advanced RISC processor, with comprehensive on-chip concurrent error detection and instruction retry, in a working single board computer. Relative to rapid, low cost testing and validation of complex fault tolerant designs, with the automated laser system at the Laser Restructuring Facility at the University of South Florida Center for Microelectronics Research (USF/CMR), a design with 10000 test points could be tested and validated in under 17 minutes. In addition to describing the successful demonstration of the technique to date, the paper discusses some of the challenges that still need to be addressed to make the technique a truly practical fault tolerant design validation tool.

System and method for supporting a fault cause analysis

Abstract: A system and method for supporting a fault cause analysis in a afault event in a plant includes a data processor with memory storing a fault model of XML files accessed by a fault cause navigator and an operating/display device. Each fault model contains an industry-specific process model divided into process steps, with steps and defined fault events needed therefor assigned to plant components/systems, and fault trees assigned to fault events and having fault hypotheses. A checklist with symptoms for verification of the fault hypothesis is assigned to the fault hypotheses. The system enables navigation to the relevant step in the process model by the display and navigator, and presents a fault event list. Following fault event selection, critical components/systems corresponding thereto are found and displayed. Possible symptoms are generated and displayed in a checklist and hypotheses of possible fault causes, contained in the fault trees, are found and displayed.

Estimating testing effectiveness of the circular self-test path technique

Abstract: The effectiveness of a random built-in self-test technique for VLSI circuits is studied. This technique, called the circular self-test path (CSTP), is applicable to circuits that consist of combinational blocks and registers. In particular, the effectiveness of test pattern generation, the effectiveness of test response compaction and fault coverage are examined. The test generation effectiveness is evaluated by the fraction of all possible test patterns applied during a testing session to the circuit under test. The compaction effectiveness of the CSTP technique is measured by the probability of aliasing, and fault coverage by the fraction of all permanent faults that are detected. For all these measures, simple formulas are developed, which give very accurate estimations without detailed circuit simulation. To demonstrate their accuracy, the estimates obtained by the formulas are compared to the results obtained by extensive simulation experiments. >