Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Testing Non-Deterministic State Machines with Fault Coverage

Abstract: The selection of appropriate test cases is an important issue in the development of communication protocols. Various test case selection methods have been developed for the case that the protocol specification is given in the form of a deterministic finite state machine (FSM). This paper present a new method which applies in the case of nondeterministic specifications and implementations. The testing process is more complex if the specification, or even the implementation, is non-deterministic. Nevertheless, under appropriate assumptions, the described test case selection method leads to a finite set of finite test cases for a given specification which guarantees that any deviation of the implementation from the specification will be detected. The paper presents the new test selection method in a framework for testing non-deterministic systems and demonstrates its use with small examples. 1. Introduction Testing plays an important role during the development of computer hardware and software. The selection of appropriate test cases is an important issue in this context. We assume in this paper that a specification of the desired behavior of the system component to be tested is available. Such a specification can be taken as the basis for the development of a suite of test cases, or for evaluating the coverage of a given test suite. This paper deals with the development of a test suite covering the behavior of a system component defined by a finite state machine specification. In contrast to most methods described in the literature, we allow for non-deterministic specifications and implementations. The issue of testing implementations in respect to a specified behavior has recently received much attention in the area of communication protocols [Rayn 87, Sari 89]. In order to validate the protocol implementation, a set of test cases, usually called a "test suite", is needed to determine whether an implementation conforms to its specification. In the case that a formal specification of the protocol is available, the test selection and fault analysis can be based on this specification [Sari 89, Boch 89m]. This paper considers the case that the specification and its implementation may have nondeterministic behaviors. We assume that both the specification and the implementation can be modelled by finite labelled transition systems. In addition to finite state machines, there are many languages which are based on (in general infinite) labelled transition systems, such as CCS [Miln 80], CSP [Hoar 85], and LOTOS [Bolo 87]. The test method described in this paper can be adapted to (subsets of) these languages. Most test selection methods for (deterministic) finite state machines [Nait 81, Chow 78, Gone 70, Sabn 88] assume that the purpose of testing is to demonstrate that the behavior of

Comparing logic coverage criteria on test case prioritization

Abstract: Logic coverage criteria have been widely used in the testing of safety-critical software. In the past few years, fault-based logic coverage criteria have been studied intensively both in theory and in practice. However, there is a lack of authentic evidence of the comparison of fault-based logic coverage criteria with other logic coverage criteria, such as branch coverage and modified condition/decision coverage (MC/DC). In this paper, we present a comprehensive empirical study that compares these logic coverage criteria on test case prioritization, which is currently a hot topic in software testing. Several useful conclusions are drawn from our research: (1) Fine-grained coverage criteria are always more effective and efficient. (2) The effectiveness of fault-based logic coverage criteria is not significantly different from that of MC/DC in terms of statistics, but the former is more stable. (3) A random strategy is more effective than branch coverage if a certain number of test cases are redundant.

The revealing power of a test case

Abstract: ‘Propagation, infection, and execution analysis’ (termed PIE) is used for predicting where faults can more easily hide in software. To make such predictions, programs are dynamically executed with test cases, and information concerning the test cases is collected into a histogram, each bin of which represents a single test case. The score in a bin predicts the likelihood that the test case will reveal a fault through the production of a failure (if a fault exists in the set of program locations that the test case executes). Preliminary experiments using program mutations suggest that the histogram technique presented in this paper can rank test cases according to their fault revealing ability.

An RT-level fault model with high gate level correlation

Abstract: With the advent of new RT-level design and test flows, new tools are needed to migrate at the RT-level the activities of fault simulation testability analysis, and test pattern generation. This paper focuses on fault simulation at the RT-level, and aims at exploiting the capabilities of VHDL simulators to compute faulty responses. The simulator was implemented as a phototypical tool, and experimental results show that simulation of a faulty circuit is no more costly than simulation of the original circuit. The reliability of the fault coverage figures computed at the RT-level is increased thanks to an analysis of inherent VHDL redundancies, and by foreseeing classical synthesis optimizations. A set of "rules" is used to compute a fault list that exhibits good correlation with stuck-at faults.

An implementation and analysis of a concurrent built-in self-test technique

Abstract: The authors propose a built-in concurrent self-test (BICST) technique for testing combinational logic circuits concurrently with their normal operation. They also introduce a concept of sharing the test hardware between identical circuits to reduce the overall area overhead. They implemented this technique in the design of an ALU (arithmetic logic unit) with online test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area, and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU. The authors define some measures for evaluating the performance of the BICST technique and discuss methods for their computation and include both simulation and analytical results. In addition to detecting permanent faults, the BICST technique can also be used for detecting intermittent and transient faults. The authors propose some methods for detecting intermittent faults and for computing the transient fault coverage. >