Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
Papers published on a yearly basis
Papers
More filters
TL;DR: In this article, basic concepts, motivation, and techniques of fault tolerance are discussed, including fault classification, redundancy techniques, reliability modeling and prediction, examples of fault-tolerant computers, and some approaches to the problem of tolerating design faults.
Abstract: Basic concepts, motivation, and techniques of fault tolerance are discussed in this paper. The topics include fault classification, redundancy techniques, reliability modeling and prediction, examples of fault-tolerant computers, and some approaches to the problem of tolerating design faults.
160 citations
20 Oct 1996
TL;DR: Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.
Abstract: This paper presents a novel test point insertion technique which, unlike the previous ones, is based on a constructive methodology. A divide and conquer approach is used to partition the entire test into multiple phases. In each phase a group of test points targeting a specific set of faults is selected. Control points within a particular phase are enabled by fixed values, resulting in a simple and natural sharing of the logic driving them. Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.
159 citations
30 Oct 2003
TL;DR: This work addresses the issue of fault tolerant chip architectures for automotive applications by reviewing fault-tolerant architectures commonly used in other industrial domains and comparing them with a metric that combines traditional terms such as cost, performance and fault coverage with flexibility.
Abstract: Fault-tolerant electronic sub-systems are becoming a standard requirement in the automotive industrial sector as electronics becomes pervasive in present cars. We address the issue of fault tolerant chip architectures for automotive applications. We begin by reviewing fault-tolerant architectures commonly used in other industrial domains where fault-tolerant electronics has been a must for a number of years, e.g., the aircraft manufacturing industrial sector. We then proceed to investigate how these architecture could be implemented on a single chip and we compare them with a metric that combines traditional terms such as cost, performance and fault coverage with flexibility, i.e. the ability of adapting to changing requirements and capturing a wide range of applications, an emerging criterion for platform design. Finally, we describe in some details a cost effective dual lock-step platform that can be used as a single fail-operational unit or as two fail-silent channels trading fault-tolerance for performance.
159 citations
TL;DR: In this paper, a procedure based on the continuous wavelet transform (CWT) for the analysis of voltage transients due to line faults, and its application to fault location in power distribution systems is discussed.
158 citations
27 Jun 1988
TL;DR: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, this article presented several concepts aiming at a further improvement and acceleration of the deterministic test pattern generator and redundancy identification process.
Abstract: Based on the sophisticated strategies used in the automatic test pattern generation system SOCRATES, the authors present several concepts aiming at a further improvement and acceleration of the deterministic test pattern generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. Both procedures significantly advance the deterministic test pattern generation and redundancy identification especially for those faults, for which it is difficult to generate a test pattern or to prove them to be redundant, respectively. As a result of the application of the proposed techniques, SOCRATES is capable of successfully generating a test pattern for all testable faults in a set of combinational benchmark circuits, and of identifying all redundant faults with less than 10 backtrackings. >
158 citations