Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
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16 Oct 2006
TL;DR: In this paper, the authors proposed a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis, and the proposed method gives rms profiles of the fault currents of interest (i.e., the fault contribution and the fault current the protective device will see) under both balanced and unbalanced fault conditions.
Abstract: Summary form only given. This paper shows that the current an inverter interfaced distributed generator (IIDG) contributes to a fault varies considerably, due mainly to fast response of its controller. The paper proposes a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis. The proposed method gives rms profiles of the fault currents of interest (IIDG contribution and the fault currents the protective device will see). Test results, based on a prototype feeder, show that the proposed approach can estimate the fault currents contributions under both balanced and unbalanced fault conditions.
124 citations
08 Nov 2005
TL;DR: A scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper is proposed, which takes advantage of the regular design of the NoC to reduce both test area overhead and test time.
Abstract: Network-on-chip has recently emerged as alternative communication architecture for complex system chip and different aspects regarding NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing faults has been marginally tackled. This paper proposes a scalable test strategy for the routers in a NoC, based on partial scan and on an IEEE 1500-compliant test wrapper. The proposed test strategy takes advantage of the regular design of the NoC to reduce both test area overhead and test time. Experimental results show that a good tradeoff of area overhead, fault coverage, test data volume, and test time is achieved by the proposed technique. Furthermore, the method can be applied for large NoC sizes and it does not depend on the network routing and control algorithms, which makes the method suitable to test a large class of network models
123 citations
28 Apr 1996
TL;DR: An overview of the most important and commonly used fault models, including the industry's popular disturb fault model, are given and a methodology to design tests for realistic linked faults is presented, resulting in the new tests March LR, March LRD and March LRDD.
Abstract: Many march tests have already been designed to cover faults of different fault models. The complexity of these tests arises when linked faults are taken into consideration. This paper gives an overview of the most important and commonly used fault models, including the industry's popular disturb fault model. The fault coverage of march tests is analysed in a novel way, i.e., in terms of their detection capabilities for: simple faults, and linked faults; whereby the infinite class of linked faults has been reduced to a set of realistic linked faults. Thereafter the paper presents a methodology to design tests for realistic linked faults, resulting in the new tests March LR, March LRD and March LRDD. These new tests will be shown to be more efficient and to offer a higher fault coverage than comparable existing tests.
122 citations
TL;DR: This analysis of the relationships between variable and literal faults, and among literal, operator, term, and expression faults, produces a richer set of findings that interpret previous empirical results, can be applied to the design and evaluation of test methods, and inform the way that test cases should be prioritized for earlier detection of faults.
Abstract: Kuhn, followed by Tsuchiya and Kikuno, have developed a hierarchy of relationships among several common types of faults (such as variable and expression faults) for specification-based testing by studying the corresponding fault detection conditions. Their analytical results can help explain the relative effectiveness of various fault-based testing techniques previously proposed in the literature. This article extends and complements their studies by analyzing the relationships between variable and literal faults, and among literal, operator, term, and expression faults. Our analysis is more comprehensive and produces a richer set of findings that interpret previous empirical results, can be applied to the design and evaluation of test methods, and inform the way that test cases should be prioritized for earlier detection of faults. Although this work originated from the detection of faults related to specifications, our results are equally applicable to program-based predicate testing that involves logic expressions.
122 citations
02 Jul 1986
TL;DR: A test generation system capable of high fault coverage in complex sequential circuits that dynamically expands to multi-path sensitization in reconvergent fan-out structures to reduce back-tracking.
Abstract: This paper describes a test generation system capable of high fault coverage in complex sequential circuits. Sequential logic is efficiently processed by a unidirectional time flow approach. This single path sensitization technique dynamically expands to multi-path sensitization in reconvergent fan-out structures. Sophisticated conflict analysis is used to reduce back-tracking. User guidance is also accepted to further improve performance.
122 citations