Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Test suite reduction with selective redundancy

Abstract: Software testing is a critical part of software development. Test suite sizes may grow significantly with subsequent modifications to the software over time. Due to time and resource constraints for testing, test suite minimization techniques attempt to remove those test cases from the test suite that have become redundant over time since the requirements covered by them are also covered by other test cases in the test suite. Prior work has shown that test suite minimization techniques can severely compromise the fault detection effectiveness of test suites. In this paper, we present a novel approach to test suite reduction that attempts to selectively keep redundant tests in the reduced suites. We implemented our technique by modifying an existing heuristic for test suite minimization. Our experiments show that our approach can significantly improve the fault detection effectiveness of reduced suites without severely affecting the extent of test suite size reduction.

Reliability of Computer Systems and Networks Fault Tolerance, Analysis, and Design

Abstract: (2003). Reliability of Computer Systems and Networks Fault Tolerance, Analysis, and Design. IIE Transactions: Vol. 35, No. 6, pp. 586-587.

DS-LFSR: a BIST TPG for low switching activity

Abstract: A test pattern generator (TPG) for built-in self-test (BIST), which can reduce switching activity during test application, is proposed. The proposed TPG, called dual-speed LFSR (DS-LFSR), consists of two linear feedback shift registers (LFSRs), a slow LFSR and a normal-speed LFSR. The slow LFSR is driven by a slow clock whose speed is 1/dth that of the normal clock, which drives the normal-speed LFSR. The use of DS-LFSR reduces the frequency of transitions at the circuit inputs driven by the slow LFSR, leading to a reduction in switching activity during test application. A procedure is presented to design a DS-LFSR so as to achieve high fault coverage by ensuring that patterns generated by it are unique and uniformly distributed. A new gain function and a method to compute its value for each circuit input are proposed to select inputs to be driven by the slow LFSR. Also, a procedure to increase the number of inputs driven by the slow LFSR by combining compatible inputs is presented to further decrease the switching activity. Finally, DS-LFSRs are designed for the ISCAS85 and ISCAS89 benchmark circuits and shown to provide a 13% to 70% reduction in the numbers of load-capacitance weighted transitions with no loss of fault coverage (for stuck-at as well as transition delay faults) and at very slight area overheads.

Timing-driven test point insertion for full-scan and partial-scan BIST

Abstract: We propose timing-driven test point insertion methods for a full-scan based BIST scheme and for a partial-scan based BIST scheme, where the global flip-flop cycles have been broken by the scan flip-flops. The objective is to minimize the performance as well as the area impact due to the insertion of test points while achieving a high fault coverage under the pseudo-random BIST scheme. The gradient-based method is used and extended to estimate the random-pattern testability improvement factors for the test point candidates of either full-scan based or partial-scan based BIST. We also propose a symbolic computation technique to compute testability for circuits under the partial-scan based BIST scheme. Experimental results show that the performance degradation of test point insertion could be unacceptably high if the cost function used for test point selection does not include the performance penalty. Using our timing-driven algorithm, zero performance degradation and a high fault coverage can always be achieved using a small number of test points.