Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Immunotronics - novel finite-state-machine architectures with built-in self-test using self-nonself differentiation

Abstract: A novel approach to hardware fault tolerance is demonstrated that takes inspiration from the human immune system as a method of fault detection. The human immune system is a remarkable system of interacting cells and organs that protect the body from invasion and maintains reliable operation even in the presence of invading bacteria or viruses. This paper seeks to address the field of electronic hardware fault tolerance from an immunological perspective with the aim of showing how novel methods based upon the operation of the immune system can both complement and create new approaches to the development of fault detection mechanisms for reliable hardware systems. In particular, it is shown that by use of partial matching, as prevalent in biological systems, high fault coverage can be achieved with the added advantage of reducing memory requirements. The development of a generic finite-state-machine immunization procedure is discussed that allows any system that can be represented in such a manner to be "immunized" against the occurrence of faulty operation. This is demonstrated by the creation of an immunized decade counter that can detect the presence of faults in real time.

A low overhead design for testability and test generation technique for core-based systems

Abstract: In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level DFT to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level DFT and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used to tackle the above problem is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on two example systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

An analytical approach to the partial scan problem

Abstract: The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.

Controlling peak power during scan testing

Abstract: This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverage. The proposed approach works for any conventional full-scan design-no extra design-for-test (DFT) logic is required. If the peak power in a clock cycle during scan testing exceeds a specified limit (which depends on the amount of peak power that can be safely handled without causing a failure that would not occur during normal functional operation) then a "peak power violation" occurs. Given a set of scan vectors, simulation is done to identify and classify the scan vectors that are causing peak power violations during scan testing. The problem scan vectors are then modified in a way that eliminates the peak power violations while preserving the fault coverage. Experimental results indicate the proposed procedure is very effective in controlling peak power.

Closure on "A new protection scheme for fault detection, direction discrimination, classification, and location in transmission lines"

Abstract: This paper presents a new adaptive fault protection scheme for transmission lines using synchronized phasor measurements. The work includes fault detection, direction discrimination, classification and location. Both fault detection and fault location indices are derived by using two-terminal synchronized measurements incorporated with distributed line model and modal transformation theory. The fault detection index is composed of two complex phasors and the angle difference between the two phasors determines whether the fault is intemal or external to the protected zone. The fault types can be classified by the modal fault detection index. The proposed scheme also combines on-line parameter estimation to assure protection scheme performance and to achieve adaptive protection. Extensive simulation studies show that the proposed scheme provides a fast relay response and high accuracy in fault location under various system and fault conditions. The proposed method responds very well with regard to dependability, security and sensitivity (high-resistance fault coverage).