Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Testing deterministic implementations from nondeterministic FSM specifications

Abstract: In this paper, conformance testing of protocols specified as nondeterministic finite state machines is considered. Protocol implementations are assumed to be deterministic. In this testing scenario, the conformance relation becomes a preorder, so-called reduction relation between FSMs. The reduction relation requires that an implementation machine produces a (sub)set of output sequences that can be produced by its specification machine in response to every input sequence. A method for deriving tests with respect to the reduction relation with full fault coverage for deterministic implementations is proposed based on certain properties of the product of specification and implementation machines.

Model-Based and Data-Driven Fault Detection Performance for a Small UAV

Abstract: Fault detection and identification algorithms may rely on knowledge of underlying system dynamics while some eschew this modeling in favor of data-driven anomaly detection. This paper considers model-based residual generation and data-driven anomaly detection for a small, low-cost unmanned aerial vehicle using both types of approaches and applies those algorithms to experimental faulted and unfaulted flight-test data. The model-based fault detection strategy uses robust linear filtering methods to reject exogenous disturbances, e.g., wind, and provide robustness to model errors. The data-driven algorithm is developed to operate exclusively on raw flight-test data without detailed system knowledge. The detection performance of these complementary, but different, methods is compared.

Securing Scan Design Using Lock and Key Technique

Abstract: Scan test has been a common and useful method for testing VLSI designs due to the high controllability and observability it provides. These same properties have recently been shown to also be a security threat to the intellectual property on a chip (Yang et al., 2004). In order to defend from scan based attacks, we present the lock & key technique. Our proposed technique provides security while not negatively impacting the design's fault coverage. This technique requires only that a small area overhead penalty is incurred for a significant return in security. Lock & key divides the already present scan chain into smaller subchains of equal length that are controlled by an internal test security controller. When a malicious user attempts to manipulate the scan chain, the test security controller goes into insecure mode and enables each subchain in an unpredictable sequence making controllability and observability of the circuit under test very difficult. We present and analyze the design of the lock & key techniques to show that this is a flexible option to secure scan designs for various levels of security