Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

A Direct Three-Phase Circuit Analysis-Based Fault Location for Line-to-Line Fault

Abstract: From a direct three-phase circuit analysis, an accurate fault-location algorithm has been obtained for the line-to-line fault as an extension of the author's previous work for line-to-ground fault location. Robustness of the proposed algorithm to load impedance uncertainty is enhanced by the introduction of impedance compensation using voltage and current measurements. Simulation results show a high degree of accuracy and robustness to load uncertainty.

Wide-Area Backup Protection Algorithm Based on Fault Component Voltage Distribution

Abstract: A new wide-area backup protection algorithm based on the fault component voltage distribution is proposed in this paper. It is helpful to overcome the problems of complex setting and maloperation under flow transfer of conventional backup protection. The measured values of fault component voltage and current at one terminal of the transmission line are applied to estimate the fault component voltage at the other terminal. Then, the fault element can be identified by the ratio between the measured values and the estimated values. In addition, the speed of fault element identification can be accelerated by a faulted area detection scheme. The proposed method has the advantage of easy setting and low requirement for synchronized wide-area data. The studies performed on the IEEE 39-bus system validate the proposed algorithm under various faults and flow transfer.

An efficient algorithm for sequential circuit test generation

Abstract: This paper presents an efficient sequential circuit automatic test generation algorithm. The algorithm is based on PODEM and uses a nine-valued logic model. Among the novel features of the algorithm are use of Initial Timeframe Algorithm and correct implementation of a solution to the Previous State Information Problem. The Initial Timeframe Algorithm, one of the most important aspects of the test generator, determines the number of timeframes required to excite the fault for which a test is to be derived and the number of timeframes required to observe the excited fault. Correct determination of the number of timeframes in which the fault should be excited (activated) and observed saves the test generator from performing unnecessary search in the input space. Test generation is unidirectional, i.e., it is done strictly in forward time, and flip-flops in the initial timeframe are never assigned a state that needs to be justified later. The algorithm saves both the good and the faulty machine states after finding a test to aid in subsequent test generation. The Previous State Information Problem, which has often been ignored by existing test generators, is presented and discussed in the paper. Experimental results are presented to demonstrate the effectiveness of the algorithm. >

A Simple Real-Time Fault Signature Monitoring Tool for Motor-Drive-Embedded Fault Diagnosis Systems

Abstract: The reference frame theory constitutes an essential aspect of electric machine analysis and control. In this study, apart from the conventional applications, it is reported that the reference frame theory approach can successfully be applied to real-time fault diagnosis of electric machinery systems as a powerful toolbox to find the magnitude and phase quantities of fault signatures with good precision as well. The basic idea is to convert the associated fault signature to a dc quantity, followed by the computation of the signal's average in the fault reference frame to filter out the rest of the signal harmonics, i.e., its ac components. As a natural consequence of this, neither a notch filter nor a low-pass filter is required to eliminate fundamental component or noise content. Since the incipient fault mechanisms have been studied for a long time, the motor fault signature frequencies and fault models are very well-known. Therefore, ignoring all other components, the proposed method focuses only on certain fault signatures in the current spectrum depending on the examined motor fault. Broken rotor bar and eccentricity faults are experimentally tested online using a TMS320F2812 digital signal processor (DSP) to prove the effectiveness of the proposed method. In this application, only the readily available drive hardware is used without employing additional components such as analog filters, signal conditioning board, external sensors, etc. As the motor drive processing unit, the DSP is utilized both for motor control and fault detection purposes, providing instantaneous fault information. The proposed algorithm processes the measured data in real time to avoid buffering and large-size memory needed in order to enhance the practicability of this method. Due to the short-time convergence capability of the algorithm, the fault status is updated in each second. The immunity of the algorithm against non-ideal cases such as measurement offset errors and phase unbalance is theoretically and experimentally verified. Being a model-independent fault analyzer, this method can be applied to all multiphase and single-phase motors.

Testing embedded cores using partial isolation rings

Abstract: Intellectual property cores pose a significant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the user-defined logic around the core. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around the core, however, the area and performance overhead for this may not be acceptable in many applications. This paper presents a systematic method for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs (that includes the critical timing paths) that do not need to be included in the partial isolation ring. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies.