Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
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26 Apr 1999
TL;DR: It is shown that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased, and a method is introduced to reduce the number of tests included in an n -detection test set by using different values of n for different faults based on their potential effect on the defect coverage.
Abstract: We study the effectiveness of n-detection test sets based on transition faults in detecting defects that affect the timing behavior of a circuit. We use path delay faults as surrogates for unmodeled defects, and show that the path delay fault coverage achieved by an n-detection transition fault test set increases significantly as n is increased. We also introduce a method to reduce the number of tests included in an n-detection test set by using different values of n for different faults based on their potential effect on the defect coverage. The resulting test sets are referred to as variable n-detection test sets.
98 citations
AT&T1
TL;DR: This approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well, and shows that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.
Abstract: In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.
98 citations
03 Oct 2000
TL;DR: Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5–15%.
Abstract: We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100 K gates with 10000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required, complete fault efficiency is guaranteed, and the impact on the design process is minimized.
98 citations
TL;DR: The theoretical analysis shows that this transparent BIST technique does not decrease the fault coverage for modeled faults, it behaves better for unmodeled ones and does not increase the aliasing with respect to the initial test algorithm.
Abstract: I present the theoretical aspects of a technique called transparent BIST for RAMs. This technique applies to any RAM test algorithm and transforms it into a transparent one. The interest of the transparent test algorithms is that testing preserves the contents of the RAM. The transparent test algorithm is then used to implement a transparent BIST. This kind of BIST is very suitable for periodic testing of RAMs. The theoretical analysis shows that this transparent BIST technique does not decrease the fault coverage for modeled faults, it behaves better for unmodeled ones and does not increase the aliasing with respect to the initial test algorithm. Furthermore, transparent BIST involves only slightly higher area overhead with respect to standard BIST. Thus, transparent BIST becomes more attractive than standard BIST since it can be used for both fabrication testing and periodic testing.
98 citations
TL;DR: The main contributions of the proposed fault location technique are to decrease the multiple estimations associated with impedance-based methods, to propose a systematic approach to build the LVZs, and to explore the presence of smart meters for fault location.
Abstract: This paper proposes to combine the voltage monitoring capability of smart meters with impedance-based fault location methods to provide an efficient fault location approach improving service restoration. The first step of the proposed methodology is to apply an impedance-based method to obtain a rough estimation of fault location. Since the result is an estimated distance to the fault, multiple branches can be indicated due to the typical distribution systems topologies. Therefore, the challenge is: how to recognize the actual fault location? To solve this problem, voltage measurements from smart meters are used to build the low voltage zones (LVZs). The main contributions of the proposed fault location technique are to decrease the multiple estimations associated with impedance-based methods, to propose a systematic approach to build the LVZs, and to explore the presence of smart meters for fault location. The proposed method was tested through intensive and extensive simulations in a real distribution system, proving its efficiency.
97 citations