Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

An improved protocol test generation procedure based on UIOS

Abstract: This paper shows the Unique Input/Output, UIO, approach and the Distinguishing Sequence, DS, approach for the conformance testing of protocol implementations do not always produce identical fault converges, contrary to a previous claim. In the UIO approach, when UIO sequences and signatures are not unique in an implementation, they may not be able to detect erroneous states in the implementation. The UIO approach is revised here with the addition of a verification procedure to ensure that the UIO sequences are all unique in an implementation. Since signatures are generally not unique, this revision requires substituting the use of a signature for a state, S, with a set of input/output sequences, IO(S,K)s, unique to S, each of which distinguishes S from at least one other state, K. Verification is then applied to the IO(S,K)s. Fault coverage in the revised UIO, UIOv, approach is better than that in the original approach. A uniqueness criterion is discussed here to capture a desirable fault coverage for finite-state machine, FSM, test sequences. This criterion ensures the detection of any faulty FSM implementation provided that its set of states does not exceed that in the specified FSM. It is shown that test sequences generated by the UIOv approach and the DS approach always satisfy the uniqueness criterion. In fact, the DS approach is a special case of the UIOv approach; however, the UIOv approach has wider applicability and is generally applicable to k-distinguishable FSMs.

Test vector modification for power reduction during scan testing

Abstract: This paper presents a test vector modification method for reducing power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 48% of the original test set.

Effects of transient gate-level faults on program behavior

Abstract: Effects of gate-level faults on program behavior are described and used as a basis for fault models at the program level. A simulation model of the IBM RT PC was developed and injected with 18900 gate-level transient faults. A comparison of the system state of good and faulted runs was made to observe internal propagation of errors, while memory traffic and program flow comparisons detected errors in program behavior. Results show several distinct classes of program-level error behavior, including program flow changes, incorrect memory bus traffic, and undetected but corrupted program state. Additionally, the dependencies of fault location, injection time, and workload on error detection coverage are reported. For the IBM RT PC, the error detection latency was shown to follow a Weibull distribution dependent on the error detection mechanism and the two selected workloads. These results aid in the understanding of the effects of gate-level faults and allow for the generation and validation of new fault models, fault injection methods, and error detection mechanisms. >

Statistical delay fault coverage and defect level for delay faults

Abstract: A quantitative delay fault coverage model is discussed to provide a figure of merit for delay testing. System sensitivity of a path to a delay fault along that path and the effectiveness of a delay test are described in terms of the propagation delay of the path under test and the delay defect size. A statistical delay fault coverage model is established. A defect-level model is also proposed as a function of the yield of a manufacturing process and the statistical delay fault coverage. >

Detecting bridging faults with stuck-at test sets

Abstract: A method is described that provides high detection of bridging faults without requiring extensive fault simulation. Bridging fault coverage can be increased by doing fault simulation and test generation for bridging faults that are identified as hard to detect. These bridging faults occur between nodes that rarely, if ever, differ, or that seldom change value. In addition, if the nodes in the fault-free circuits toggle often, feedback faults are easier to detect. This is true even if the nodes involved always have equal values. Methods for identifying such nodes have been presented. These methods use results available from fault-free simulations. A simple solution is to randomly reorder the test vectors to increase toggling and therefore increase bridging fault coverage. As a result, computer time for test generation will be only slightly greater than the time required for stuck-at fault generation alone. >