Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
Papers published on a yearly basis
Papers
More filters
Patent•
22 Mar 2002
TL;DR: In this paper, a method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where each domain has a plurality of scan cells is presented.
Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks
84 citations
TL;DR: In this article, the authors proposed a method for real-time monitoring and fault diagnosis in photovoltaic systems, which is based on a comparison between the performances of a faulty PV module, with its accurate model by quantifying the specific differential residue that will be associated with it.
83 citations
TL;DR: The work presented in this paper involves building an effective fault prediction tool by identifying and investigating the predictive power of several well-known and widely used software metrics for fault prediction by using Least Squares Support Vector Machine learning method associated with linear, polynomial and radial basis function kernel functions.
83 citations
IBM1
TL;DR: A new method of simultaneously generating exhaustive test patterns for all possible input subsets up to a specified size is proposed and can be easily implemented by modifying existing shift-registers in an LSSD or scan path design to embody additional feedback connections.
Abstract: Logic testing of today's integrated circuits is a task of increasing difficulty as the number of circuits or transistors packed onto a single chip grows higher and higher. Exhaustive pattern testing, with adequate partitioning of logic, has been explored regarding its potential in solving the problems in test pattern generation and fault coverage. In this paper, we propose a new method of simultaneously generating exhaustive test patterns for all possible input subsets (each corresponding to an output) up tq a specified size. The method is based on the structure of linear polynomial codes and can be easily implemented by modifying existing shift-registers in an LSSD or scan path design to embody additional feedback connections. This is particularly attractive since the implementation is compatible with the approach of self-testing using pseudorandom patterns. Thus, a very reasonable strategy is to combine limited exhaustive pattern testing with pseudorandom pattern testing ini cases where complete exhaustive testing is not practical.
83 citations
01 Jul 1993
TL;DR: New cost-effective heuristics for the generation of small test sets and an improved procedure for computing independent fault sets which are used to selecet target faults in test generation are proposed.
Abstract: New cost-effective heuristics for the generation of small test sets are introduced, and heuristics proposed previously are enhanced. An improved procedure is also proposed for computing independent fault sets which are used to selecet target faults in test generation. The procedure results in large lower bounds on the minimum test set size. Experimental results of test generation demonstrate the effectiveness of the heuristics.
83 citations