Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
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23 Jun 1998
TL;DR: The description and application of the features of MEFISTO-L, the fault injection tool for VHDL models, being developed at LAAS, are described for supporting the strategy that is proposed for testing FTMs.
Abstract: The early assessment of the adequacy of fault tolerance mechanisms (FTMs), and the subsequent removal of fault tolerance deficiency faults (ftd-faults), are essential tasks in the design process of dependable computer systems. The paper is centered on the description and application of the features of MEFISTO-L, the fault injection tool for VHDL models, being developed at LAAS for supporting the strategy that we have proposed for testing FTMs. The paper first describes the overall testing framework in which MEFISTO-L is incorporated. The main guidelines for the design of MEFISTO-L and its objectives, attributes, implementation and use are then described. Special attention is given to the main original and innovative features: i) the embedded VHDL code analyzer, ii) the observation and injection mechanisms, iii) their synchronization, and iv) their automatic placement in the target VHDL model.
82 citations
Proceedings Article•
01 Jan 1990
TL;DR: In this paper, simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I, testing for stuck-at faults, which will detect logically redundant and multiple stuck at faults and improve the detection of non-stuck-at fault defects.
Abstract: Simplified ATPG and fault simulation algorithms, reduced test set sizes, and increased fault coverage are achieved with I, testing for stuck-at faults. In addition, IDm testing will detect logically redundant and multiple stuck-at faults and improve the detection of non-stuck-at fault defects.
82 citations
04 Nov 2009
TL;DR: A verification methodology to assess the correctness of Simulink programs by means of automated test-case generation and several optimisations are discussed to make the approach practical for realistic Simulinks programs and fault models, and to obtain accurate coverage measures.
Abstract: The Matlab/Simulink language has become the standard formalism for modeling and implementing control software in areas like avionics, automotive, railway, and process automation. Such software is often safety critical, and bugs have potentially disastrous consequences for people and material involved. We define a verification methodology to assess the correctness of Simulink programs by means of automated test-case generation. In the style of fault- and mutation-based testing, the coverage of a Simulink program by a test suite is defined in terms of the detection of injected faults. Using bounded model checking techniques, we are able to effectively and automatically compute test suites for given fault models. Several optimisations are discussed to make the approach practical for realistic Simulink programs and fault models, and to obtain accurate coverage measures.
82 citations
06 May 2014
TL;DR: This paper presents a survey on the simulation-based fault injection techniques, with a focus on complex micro-processor based systems.
Abstract: Dependability is a key decision factor in today's global business environment. A powerful method that permits to evaluate the dependability of a system is the fault injection. The principle of this approach is to insert faults into the system and to monitor its responses in order to observe its behavior in the presence of faults. Several fault injection techniques and tools have been developed and experimentally tested. They could be mainly grouped into three categories: hardware fault injection, simulation-based fault injection, and emulation-based fault injection. This paper presents a survey on the simulation-based fault injection techniques, with a focus on complex micro-processor based systems.
82 citations
TL;DR: It is shown that parallel processing of HTD faults does indeed result in high fault coverage, which is otherwise not achievable by a uniprocessor algorithm, and the parallel algorithm exhibits superlinear speedups in some cases due to search anomalies.
Abstract: For circuits of VLSI complexity, test generation time can be prohibitive. Most of the time is consumed by hard-to-detect (HTD) faults, which might remain undetected even after a large number of backtracks. The problems inherent in a uniprocessor implementation of a test generation algorithm are identified, and a parallel test generation method which tries to achieve a high fault coverage for HTD faults in a reasonable amount of time is proposed. A dynamic search space allocation strategy which allocates disjoint search spaces to minimize the redundant work is proposed. The search space allocation strategy tries to utilize the partial solutions generated by other processors to increase the probability of searching in a solution area. The parallel test generation algorithm has been implemented on an Intel iPSC/2 hypercube. It is shown that parallel processing of HTD faults does indeed result in high fault coverage, which is otherwise not achievable by a uniprocessor algorithm. The parallel algorithm exhibits superlinear speedups in some cases due to search anomalies. >
82 citations