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Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.


Papers
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Proceedings ArticleDOI
01 Jan 1990
TL;DR: An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault, demonstrating that drastic reductions in test time can be achieved without sacrificing fault coverage.
Abstract: Given the high cost of testing analog circuit functionality, it is proposed that tests for analog circuits should be designed to detect faults. An algorithm is presented that reduces functional test sets to only those that are sufficient to find out whether a circuit contains a parametric fault. Examples demonstrate that drastic reductions in test time can be achieved without sacrificing fault coverage. >

80 citations

Journal ArticleDOI
TL;DR: In this paper, a general architecture for fault tolerant control is proposed based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBJ parameterization to quantify the performance of the fault tolerant system.
Abstract: A general architecture for fault tolerant control is proposed. The architecture is based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBK parameterization to quantify the performance of the fault tolerant system. The approach suggested can be applied for additive faults, parametric faults and for system structural changes. The modelling for each of these fault classes is described. The method allows for design of passive as well as for active fault handling. Also, the related design method can be fitted either to guarantee stability or to achieve graceful degradation in the sense of guaranteed degraded performance. A number of fault diagnosis problems, fault tolerant control problems, and feedback control with fault rejection problems are formulated/considered, mainly from a fault modelling point of view. The method is illustrated on a servo example including an additive fault and a parametric fault.

80 citations

Proceedings ArticleDOI
26 Oct 1991
TL;DR: A two-stage procedure for locating V LSI faults is presented and an industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two- stage fault location was measured.
Abstract: A two-stage procedure for locating VLSI faults is presented. The approach utilizes dynamic fault dictionaries, test set partitioning, and reduced fault lists to achieve a reduction in size and complexity over classic static fault dictionaries. An industrial implementation is reported in which faults were injected and diagnosed in a VLSI chip and the perjiormunce of two-stage fault location was measured.

79 citations

Proceedings ArticleDOI
30 Oct 2001
TL;DR: An automatic test pattern generation (ATPG) method is presented for a scan-based test architecture which minimizes ATE storage requirements and reduces the bandwidth between the automatic test equipment and the chip under test.
Abstract: An automatic test pattern generation (ATPG) method is presented for a scan-based test architecture which minimizes ATE storage requirements and reduces the bandwidth between the automatic test equipment (ATE) and the chip under test. To generate tailored deterministic test patterns, a standard ATPG tool performing dynamic compaction and allowing constraints on circuit inputs is used. The combination of an appropriate test architecture and the tailored test patterns reduces the test data volume up to two orders of magnitude compared with standard compacted test sets.

79 citations

Proceedings ArticleDOI
18 Oct 1998
TL;DR: It is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator.
Abstract: Most built-in self test (BIST) solutions require specialized test pattern generation hardware which may introduce significant area overhead and performance degradation. Recently, some authors proposed test pattern generation on chip by means of functional units also used in system mode like adders or multipliers. These schemes generate pseudo-random or pseudo-exhaustive patterns for serial or parallel BIST. If the circuit under test contains random pattern resistant faults a deterministic test pattern generator is necessary to obtain complete fault coverage. In this paper it is shown that a deterministic test set can be encoded as initial values of an accumulator based structure, and all testable faults can be detected within a given test length by carefully selecting the seeds of the accumulator. A ROM is added for storing the seeds, and the control logic of the accumulator is modified. In most cases the size of the ROM is less than the size required by traditional LFSR-based reseeding approaches.

79 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202360
2022135
202167
202089
2019120
2018151