Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.

Systematic software-based self-test for pipelined processors

Abstract: Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs. We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15% (12% on average) for the entire processor, and fault coverage improvements of 22% for the pipeline logic, compared to a conventional SBST approach.

Transmission-Line Fault Analysis Using Synchronized Sampling

Abstract: An automated analysis approach, which can automatically characterize fault and subsequent relay operation, is the focus of this paper. It utilizes synchronized samples captured during transients from both ends of the transmission line to detect, classify, and locate transmission-line faults and can verify that the tripped line has indeed experienced a fault. The proposed method is tested for several faults simulated on an IEEE 118-bus test system and it has been concluded that it can detect and classify a fault using prefault and postfault recorded samples within 7 ms of fault inception and can accurately locate a fault with 3% accuracy. This time response performance is highly desirable since with the increasing use of modern circuit breakers, which can open the faulty line in less than two cycles, the time window of the captured waveforms is significantly reduced due to the unavailability of measurement signals after breakers open.

ATPG for ultra-large structured designs

Abstract: A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described This system is formed by optimally combining a fast fault simulator with a powerful test generator For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates >

An architecture for fault detection and isolation based on fuzzy methods

Abstract: Model-based fault detection and isolation (FDI) is an approach with increasing attention in the academic and industrial fields, due to economical and safety related matters. In FDI, the discrepancies between system outputs and model outputs are called residuals, and are used to detect and isolate faults. This paper proposes a model-based architecture for fault detection and isolation based on fuzzy methods. Fuzzy modeling is used to derive nonlinear models for the process running in normal operation and for each fault. When a fault occurs, fault detection is performed using the residuals. Then, the faulty fuzzy models are used to isolate a fault. The FDI architecture proposed in this paper uses a fuzzy decision making approach to isolate faults, which is based on the analysis of the residuals. Fuzzy decision factors are derived to isolate faults. An industrial valve simulator is used to obtain several abrupt and incipient faults, which are some of the possible faults in the real system. The proposed fuzzy FDI architecture was able to detect and isolate the simulated abrupt and incipient faults.

A method of fault simulation based on stem regions

Abstract: An exact fault simulation can be achieved by simulating only the faults on reconvergent fan-out stems, while determining the detectability of faults on other lines by critical path tracing within fan-out-free regions. The authors have delimited, for every reconvergent fan-out stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected on the line and the line is critical with respect to a primary output, then the stem fault is detected at that primary output. Any fault simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. The concept of stem regions has been used as a framework for an efficient fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis for single- as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. The simulation algorithm is described, and experimental results are shown for the well-known benchmark circuits. >