Topic
Fault coverage
About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.
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29 Jan 2002TL;DR: It will be shown that the required data backgrounds are fault model, and hence, also test specific, and industrial results will show the influence of the used data backgrounds on the fault coverage of the tests.
Abstract: The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a large impact on the effectiveness of the used tests. This paper presents an analysis of address and data scrambling for memory chips, at the layout and at the electrical level. A method is presented to determine the data backgrounds to be used for the different memory tests. It will be shown that the required data backgrounds are fault model, and hence, also test specific. Industrial results will show the influence of the used data backgrounds on the fault coverage of the tests.
76 citations
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TL;DR: A novel wide area backup protection algorithm to identify fault branch based on the fault steady state component is proposed and the simulation results for the 10-generator 39-bus system verify that this method is able to easily identify fault Branch with limited measurement points.
Abstract: A novel wide area backup protection algorithm to identify fault branch based on the fault steady state component is proposed. Under normal conditions of the power system, subsets of buses called protection correlation regions (PCRs) are formed on the basis of the network topology and phasor measurement unit (PMU) placement. After the fault occurs, by analyzing the fault steady state component of differential current in each PCR, the fault correlation region is confirmed and then a fault correlation factor (FCF), is calculated in real time to locate the fault branch. The simulation results for the 10-generator 39-bus system verify that this method is able to easily identify fault branch with limited measurement points.
75 citations
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TL;DR: The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation.
Abstract: Fault simulation of a test set in an order different from the order of generation (e.g., reverse- or random-order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. We propose an improvement to this type of fault simulation process that makes it even more effective in reducing the test-set size. The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation. We present experimental results to demonstrate the effectiveness of the proposed improvement.
75 citations
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TL;DR: Two procedures are presented for generating fault detection test sequences for large sequential circuits using an adaptive random procedure and an algorithmic path-sensitizing procedure that employs a three-valued logic system.
Abstract: Two procedures are presented for generating fault detection test sequences for large sequential circuits. In the adaptive random procedure one can achieve a tradeoff between test generation time, length, and percent of circuit tested. An algorithmic path-sensitizing procedure is also presented. Both procedures employ a three-valued logic system. Some experimental results are given.
75 citations
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20 Sep 1992
TL;DR: A diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults is described, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes.
Abstract: In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.
74 citations