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Fault coverage

About: Fault coverage is a research topic. Over the lifetime, 10153 publications have been published within this topic receiving 161933 citations. The topic is also known as: test coverage.


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Proceedings ArticleDOI
09 Jun 2009
TL;DR: In this article, a new approach for determining the exact fault type and location in distribution systems including distributed generation using MLP neural networks is presented, after determining the fault type, by normalizing the fault current of the main source, the corresponding trained neural network has been activated and the exact location of occurred fault has been derived.
Abstract: Finding and designing new methods for determining type and exact location of faults in power system has been a major subject for power system protection engineers in recent years. Fault locating in transmission networks is not very hard and complicated due to low impedance of faults. This job is usually done by distance relays. But, in distribution networks, because of high impedance of fault and its vast variety and also simplicity of protective devices, determining the exact location of faults is very complicated. On the other hand, penetration of distribution generation into distribution networks reinforces the necessity of designing new protection systems for these networks. One of the main capabilities that can improve the efficiency of new protection relays in distribution systems is exact fault locating. In this paper, a new approach for determining the exact fault type and location in distribution systems including distributed generation using MLP neural networks is presented. In the suggested method, after determining the fault type, by normalizing the fault current of the main source, the corresponding trained neural network has been activated and the exact location of occurred fault has been derived. The presented method has been implemented on a sample distribution network, simulated by DIgSILENT Power Factory 13.2, and its performance has been tested. The simulation results show high performance and accuracy of the method and substantiate that it can be used in modern heuristic protection schemes in distribution systems.

71 citations

Proceedings ArticleDOI
30 Oct 2001
TL;DR: The study focuses on the location and distribution of probable bridging defects and attempts to explain the findings in the context of the characteristics of the design and its implementation.
Abstract: Presents an experimental study of bridging fault locations on the Intel Pentium (TM) 4 CPU as determined by an inductive fault analysis tool. The study focuses on the location and distribution of probable bridging defects and attempts to explain the findings in the context of the characteristics of the design and its implementation. The coverage obtained against these faults by manually generated functional patterns is compared against that achieved by ATPG vectors.

71 citations

Journal ArticleDOI
TL;DR: This paper focuses on the studies of fault detection, fault classification, fault location, fault phase selection, and fault direction discrimination by using artificial neural networks approach.
Abstract: Contemporary power systems are associated with serious issues of faults on high voltage transmission lines. Instant isolation of fault is necessary to maintain the system stability. Protective relay utilizes current and voltage signals to detect, classify, and locate the fault in transmission line. A trip signal will be sent by the relay to a circuit breaker with the purpose of disconnecting the faulted line from the rest of the system in case of a disturbance for maintaining the stability of the remaining healthy system. This paper focuses on the studies of fault detection, fault classification, fault location, fault phase selection, and fault direction discrimination by using artificial neural networks approach. Artificial neural networks are valuable for power system applications as they can be trained with offline data. Efforts have been made in this study to incorporate and review approximately all important techniques and philosophies of transmission line protection reported in the literature till June 2014. This comprehensive and exhaustive survey will reduce the difficulty of new researchers to evaluate different ANN based techniques with a set of references of all concerned contributions.

71 citations

Journal ArticleDOI
TL;DR: A fast fault simulation approach based on ordinary logic emulation that reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults.
Abstract: A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator.

71 citations

Proceedings ArticleDOI
28 Apr 2002
TL;DR: A novel and efficient test relaxation technique for combinational and full-scan sequential circuits is proposed that is faster than the brute-force test relaxation method by several orders of magnitude.
Abstract: Reducing test data size is one of the major challenges in testing systems-on-a-chip. This problem can be solved by test compaction and/or compression techniques. Having a partially specified or relaxed test set increases the effectiveness of test compaction and compression techniques. In this paper we propose a novel and efficient test relaxation technique for combinational and full-scan sequential circuits. The proposed technique is faster than the brute-force test relaxation method by several orders of magnitude. The application of the technique in improving the effectiveness of test compaction and compression is illustrated.

71 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202360
2022135
202167
202089
2019120
2018151