Showing papers on "Fault detection and isolation published in 1976"

Truth-Table Verification of an Iterative Logic Array

Abstract: This paper studies the problem of fault detection in iterative logic arrays (ILA's) made up of combinational cells arranged in a one-dimensional configuration with only one direction for signal propagation. It is assumed that a fault can change the behavior of the basic cell of the array in an arbitrary way, as long as the cell remains a combinational circuit. It is further assumed that any number of cells can be faulty at any time. In this way, testing an array is equivalent to verifying the correctness of its truth table. That could be done exhaustively through the application of a set of tests whose size is exponential in N, the number of cells in the array. The procedure presented in this paper generates a test set whose size is constant (i.e., independent of the number N of cells in the array). Conditions (on the structure of the basic cell) for the application of this procedure are presented. A practical example illustrating the application of this procedure is presented. Bounds for the size of the derived test set are presented and it is shown how to modify the basic cell of an arbitrary array in order to test it with a constant number of tests.

Fault detection and system for electrostatographic machines

Abstract: A xerographic type copying or reproduction machine incorporating a programmable controller to operate the various machine components in an integrated manner to produce copies is disclosed. The controller carries a master program bearing machine operating parameters from which an operating program for the specific copy run desired is formed and used to operate the machine components to produce the copies programmed. A fault flag array is routinely scanned, each flag comprising the array being associated with an operating component or area of such machine such that on a fault or malfunction thereof, the fault flag corresponding thereto is set. On detection of a fault flag, a machine fault is declared. Display means are provided to visually identify the fault location. A permanent record of certain faults and machine operations are stored in memory for future use.

About Random Fault Detection of Combinational Networks

Abstract: Fault detection by applying a random input sequence simultaneously to a network under test and to a reference network is conside-red. A distinction between testing quality and detection quality is given. The detection surface is introduced as a characteristic parameter of a combinational network. The results are applied to TTL combinational circuits.

Non-logic printed wiring board test system

Abstract: OF THE DISCLOSURE An automatic printed circuit board tester to test printed circuit boards and diagnose faults in digital and analog elect-rical circuit networks is disclosed. The system is comprised of control, stimuli, and interconnection networks in combina-tion with measuring instrumentation. For automated fault isola-tion, a moving probe assembly driven by stepping motors con-trolled by a minicomputer is utilized. The fault isolation system establishes a fault ?ath from an output pin to a terminal point within the network. The location of the terminal point together with a directed graph is utilized to select branches that could cause the failure.

On Monte Carlo Testing of Logic Tree Networks

Abstract: It is shown that by a proper selection of the probabilities of 0 and 1 at the inputs, the efficiency of random test generation can be improved. This correspondence includes some results describing the testing of actual logic networks used in a computer.

A Module-Level Testing Approach for Combinational Networks

Abstract: A module-level testing approach for combinational networks which employs hardware modification and a simplified test generation procedure is described. The approach is based on a directed graph model for the network derived at the module level. The objectives of the approach are to deal with testing directly at the module level, to use cataloged tests for the modules in the network environment, and to generate a fault detection test set with "good" fault location capability. Networks which consist of single-output modules are treated initially and then the results are extended to networks which consist of multiple-output modules. Hardware modification and test generation procedures are illustrated.

Anti skid fault detection circuit

Abstract: Fault detection circuit which is intended to be included in an anti-skid control system for a braking system of a motor vehicle. The fault detection circuit is coupled between the sensor coil and tachometer portion of the anti-skid control system and detects if the sensor coil becomes: open circuited, shorted to ground, or shorted to a power supply. If any of the aforementioned conditions arise, the fault detection circuit provides an output signal for indicating such a condition to warn the driver of the vehicle that the anti-skid control system is non operative. A low pass RC filter is utilized to limit the input signal amplitude developed across the sensor coil to a constant value which is determined by the time constant of the low pass filter. Upper and lower references voltages can be established and compared to the filter input signal to indicate failure if this voltage developed across the sensor coil approaches either the upper or lower reference voltage.

Continuous calibration system and method for analytical instruments

Abstract: A continuous automatic calibration system and fault detection method for analytical instruments of the kind used for measuring constituents of a fluid sample which system includes a memory for storing reference information, a comparator circuit for continuously comparing the instrument output to the stored reference information, and a sample-and-hold circuit charged positive or negative by the comparator, depending whether or not the instrument output exceeds the value of the reference information. The output of the sample-and-hold circuit in turn is coupled to the instrument continuously to adjust its output to correct value. Where the maximum allowed corrective range of the sample-and-hold circuit is exceeded by the signal from the comparator circuit beyond a predetermined time period, the system displays fault, warning the operator.

The application of cepstrum technique in power cable fault detection

Abstract: A technique for detecting power cable fault is described. The cable faults are usually characterized by degradation of the dielectric, either by water inclusion or physical cracking and associated voids. Voltage reflected at the fault is modeled as distorted echo. In this technique, a voltage step test signal propagates down the line and reflects energy when a change in impedance occurs. Digitized samples are taken along the return waveform. The power cepstrum of the data is then computed; a simple echo of delay τ produces a ripple in the cepstrum domain of quefrency τ yielding information about the fault location.

A reliable dual-redundant sensor FDI system for the NASA F8C-DFBW aircraft

Abstract: In this paper we outline the structure of a sensor failure detection and identification (FDI) system designed for the NASA F8C DFBW aircraft. The system is for use in a dualredundant environment, and it takes maximal advantage of all functional and kinematic relationships among the sensed variables. The technique is reliable in that we have designed the system to account for a variety of unmodeled effects and have introduced a new concept - the quality sequential probability ratio (QSPR) - that provides a useful measure of our confidence in each test. The methodology used for determining detector parameters and the "outer loop logic" for combining the various sources of information are described.

Single stuck-type fault detection in multi-valued combinational circuits

Abstract: This paper examines the problem of detecting single stuck-type faults in multi-valued combinational circuits. The algebra employed is the generalized ternary algebra developed by Vranosic, Lee and Smith. Many of the concepts already developed for fault detection in binary circuits generalize easily to the multi-valued case. However, the special properties of multi-valued circuits complicate fault detection. Specifically, this paper introduces the concept of a partially enabled gate, K-paths in combinational circuits, and suggests a modified D-algorithm for fault detection in multi-valued circuits.

Current differential fault detection circuit

Abstract: A current differential fault detection circuit. This circuit is used with a plurality of main current transformers respectively coupled to a plurality of separate conductors through which current flows into and out of a sectionalized portion of an a-c electric power system. The secondary windings of the main current transformers are connected in parallel with one another. A normally non-conducting solid state a-c switch is connected in series with the primary winding of an auxiliary transformer and the series combination is connected in parallel with the secondary windings of the main current transformers. Circuit means is provided for sensing the voltage across the secondary windings of the main current transformers. When the secondary winding voltage exceeds a predetermined level the a-c switch is triggered into conduction thereby allowing the fault current to flow through the primary winding of the auxiliary transformer. Circuitry connected to the secondary winding of the auxiliary transformer senses the fault current level and produces an output when the fault current exceeds a predetermined level.

Fault isolation in communications circuits

Abstract: In a multipoint data communications system in which a central processing unit communicates with a plurality of remote terminals over a shared two-way communications facility, an automatic fault isolation circuit is provided to monitor energy levels originating at the several remote terminals. One or more energy level thresholds are incorporated into bridging locations through which incoming and outgoing address and message signals are distributed to, and collected from, remote terminals by way of the shared facility for the purposes of detecting noise buildups and isolating trouble conditions automatically without human intervention.

Specific failure identification algorithms for the F-8

Abstract: Analytical redundancy is applied to the pitch axis of an aircraft to enhance sensor fault detection. Three different designs based on monitoring Kalman filter residuals or likelihood functions were developed. Sensor failures were simulated to evaluate the performance of the algorithms on a non-linear simulation of an F-8C aircraft. Based on requirements for sensor fault detection and preliminary simulator performance it is concluded that these algorithms have the potential for reducing the level of sensor redundancy in a digital flight control system without compromising performance.

Algebraic Properties of Functions Affecting Optimum Fault-Tolerant Realizations

Abstract: When a specific type of network is required, the function to be realized limits the amount of fault tolerance that can be achieved. Parameters of functions that affect the maximum obtainable fault tolerance and the maximum obtainable diagnosability are investigated for several types of combinational memoryless) networks.

An analytic technique for router comparison

Abstract: Design automation of electronic systems is generally separated into a number of distinct areas of effort. Breuer [1] has divided design automation into the areas of logic synthesis, gate simulation, partitioning, placement, routing, and fault detection and diagnosis. While this separation may not be complete or entirely accurate, these functions generally must be performed.

Fault-Tolerant Computing: A Introduction

Abstract: THE field of fault-tolerant computing is concerned with the analysis, design, verification, and diagnosis of computing systems that are subject to faults. A "computing system," in this general context, can be a hardware system, a software system, or a computer which includes both hardware and internal software. A "fault" can reside in either hardware or software and can occur in the process of designing and implementing the system, or in the process of using the system once it is implemented. Major areas of technical interest include: 1) the design and analysis of computers which are able to execute specified algorithms correctly (according to specified correctness criteria) in the presence of hardware and/or software faults; 2) the testing and verification of the initial correctness of hardware and software systems prior to utilization; 3) the design and implementation of on-line fault detection, fault location, and system reconfiguration procedures that can be used to recover from hardware and software faults, to perform system maintenance, and to maintain security; and 4) the development of models, measures, and techniques for evaluating the reliability, availability and, in general, the effectiveness of fault-tolerant computing systems.

Fault-Tolerant Microprogrammed Digital Controller Design

Abstract: Efficient encoding schemes for partitioning the control Read-Only Memory (ROM) of a microprogrammed digital controller into the composition of smaller ROM matrices are given in this paper. Based on these partition methods, we propose an economical way of implementing the hybrid redundant structure in a microprogrammed control for enhancing fault-tolerant control operations. The approach greatly reduces the control memory requirements, improves the ROM encoding efficiency and facilitates microprogram debugging and fault detection capabilities in the ROM's.

Fault detection in digital filter systems

Abstract: The use of a parameter identification procedure to detect faults in hardware used to implement a broad class of linear algorithms defined as digital filters is presented. Using the filter coefficient estimates produced by the identifier, a method of measuring the acceptability of the filtering algorithm is suggested and a numerical example is given.

Fault detection and alarm circuit for measuring instruments - uses control loop detector with delayed disturbance indication

Abstract: The fault detection and indication circuit is connected in parallel with the output of the measuring device. The detector input is connected to a comparator together with the output of an integrator, the resulting signal passes to an amplitude discriminator whose output is fed back to the integrator and also to a detector circuit. Output signal from the detector energises the coil of a slugged relay. A relay contact opens and closes an indicator or alarm circuit. Depending upon the nature of the signal in the control loop, the relay will either remain energised to keep the indicator on to show normal working or, after a set delay, will drop out to extinguish the lamp to indicate a fault condition.

A review of fault detection methods for large systems

Abstract: A critique is made of current research into practical fault finding procedures for the maintenance of complex engineering systems. The half split and other methods currently in practice are analysed and their main weakness shown to be that no account is taken of the various costs involved. Also analysed are cost conscious methods which are useful in diagnosis training or in designing fault detection guides. A brief look is taken at advanced diagnostic techniques which are aided by an on-line computer in selecting the next test to be made.

The Theta-lnvariant Signature Algorithm (TISA) for Incipient Failure Detection in Cyclic Machines*

Abstract: High reliability and high availability are perhaps two of the most stringent demands made upon modern complex cyclic machines. Early detection and diagnosis of incipient machine failures, can lead to significant reductions in maintenance and repair costs, and ensure reliable operation of machines such as nuclear generating power plant in a complex operating environment. A most commonly used screening and fault detection method employs the spectral analysis of machine vibrations; usually the low frequency vibration signals obtained using velocity transducers are processed. In this paper, it is shown that conventional methods often fail to identify incipient failures, i.e., the statistical accuracy and the sensitivity of classical methods to incipient failure is poor. A signature analysis called the “θ-Invariant Signature Algorithm“ (TISA) is developed and several algorithms based upon this TISA approach are presented. The statistical sensitivities of TISA algorithms and conventional signature methods are c...

The AN/BRN‐5 Loran Receiver

Abstract: The AN/BRN-5 is a part of the Poseidon upgrading of the Ballistic Missile submarine fleet as a replacement for the aging and obsolescent AN/WPN-3. In this application, it is required to have better performance and higher reliability than any existing Loran receiver. The BRN-5 is actually only a sensor, in that the data processing, filtering and logic functions are performed in the CP-890/UYK Central Navigation Computer. The hardware and software requirements are set by the performance required, which specifies search and settle times, track accuracy in noise and both synchronous and non–synchronous interferences, skywave rejection and a variety of other requirements. In addition, it is required to have an automatic overall self test capability, automatic fault isolation and a manual diagnostic mode. The system performance specification emphasizes reliability above all, not just hardware, but in the sense of accurate position information under the most severe signal environment conditions. Because of the particularly stringent signal processing requirements, some techniques not generally employed in Loran receivers were utilized. This paper describes some of these techniques, along with parameter tradeoffs and unexpected phenomena uncovered in the course of system debug.

Counter system possessing performance of fault detection

Abstract: PURPOSE:Counter system capable of executing fault detection without break of counting action by method that two counters compute counting pulses and fault diagnosis pulses one another.

An Integrated Circuit Fault Model for Digital Systems.

Abstract: : A model for the faulty behavior of digital networks realized using integrated circuit devices is proposed This model, the pin fault assumption, is based on a study of the most frequently encountered failure mechanisms for such networks, and the observation that previous fault assumptions model a large number of faults which occur with low frequency The basis for the pin fault model, and an investigation of multiple fault detection using this model are presented Fault detection for combinational modules is investigated, and it is shown that multiple pin fault detection test sets for such modules may be quite easily generated The computation required to generate such test sets is independent of the circuit realization internal to the model, and each test generated requires about the same amount of computation The computational complexity of test generation is greatly reduced compared to that for previously studied fault models Pin fault detection experiments for sequential machines are studied, and methods for designing such experiments are developed These design methods are compared to those under other fault assumptions, and a substantial reduction is observed in the length of such sequences and the computation required to produce them (Author)

Information and display requirements for independent landing monitors

Abstract: The ways an Independent Landing Monitor (ILM) may be used to complement the automatic landing function were studied. In particular, a systematic procedure was devised to establish the information and display requirements of an ILM during the landing phase of the flight. Functionally, the ILM system is designed to aid the crew in assessing whether the total system (e.g., avionics, aircraft, ground navigation aids, external disturbances) performance is acceptable, and, in case of anomaly, to provide adequate information to the crew to select the least unsafe of the available alternatives. Economically, this concept raises the possibility of reducing the primary autoland system redundancy and associated equipment and maintenance costs. The required level of safety for the overall system would in these cases be maintained by upgrading the backup manual system capability via the ILM. A safety budget analysis was used to establish the reliability requirements for the ILM. These requirements were used as constraints in devising the fault detection scheme. Covariance propagation methods were used with a linearized system model to establish the time required to correct manually perturbed states due to the fault. Time-to-detect and time-to-correct requirements were combined to devise appropriate altitudes and strategies for fault recovery.

Synthesis and Analysis of a Cost Effective, Ultrareliable, High Speed, Semiconductor Memory System

Abstract: This paper provides a detailed synthesis and analysis of a cost effective, ultrareliable, high speed, semiconductor memory system. The memory system has the capability of detecting and correcting over 99% of all single faults. The memory cycle time of 250 ns is not compromised unless a fault is encountered. The increase in circuitry for the fault-tolerent system, over the simplex system, is less than 20%. These results have been achieved through the use of special coding implementations, virtual codes, and selective redundance.