Showing papers on "Fault detection and isolation published in 1980"

A comparison connection assignment for diagnosis of multiprocessor systems

Abstract: A comparison method for diagnosis of multiprocessor systems is introduced. Given a system of n units modeled by a linear graph, problems of finding the minimum number of comparison edges required for fault detection and fault location are solved by the use of a covering algorithm. The bounds for the number of comparison edges, the number of necessary comparisons and test cycles in fault detection and fault location in systems with n units are determined and an algorithm for an optimal comparison connection assignment is given. Simplicity and ease of implementation make the described method applicable for fault detection and location in multiprocessor systems.

Test Generation for Microprocessors

Abstract: The goal of this paper is to develop test generation procedures for testing microprocessors in a user environment. Classical fault detection methods based on the gate and flip-flop level or on the state diagram level description of microprocessors are not suitable for test generation. The problem is further compounded by the availability of a large variety of microprocessors which differ widely in their organization, instruction repertoire, addressing modes, data storage, and manipulation facilities, etc. In this paper, a general graph-theoretic model is developed at the register transfer level. Any microprocessor can be easily modeled using information only about its instruction set and the functions performed. This information is readily available in the user's manual. A fault model is developed on a functional level quite independent of the implementation details. The effects of faults in the fault model are investigated at the level of the graph-theoretic model. Test generation procedures are proposed which take the microprocessor organization and the instruction set as parameters and generate tests to detect all the faults in the fault model. The complexity of the test sequences measured in terms of the number of instructions is given. Our effort in generating tests for a real microprocessor and evaluating their fault coverage is described.

Repeatered, multi-channel fiber optic communication network having fault isolation system

Abstract: A repeatered, multichannel fiber optic communication network includes a plurality of full duplex fiber optic channels and one or more auxiliary channels. In order to supervise and control the operation of the network, for both data transmission and fault/maintenance actions, each terminal station contains a processor-based subsystem capable of network monitoring, first level maintenance action, fault isolation, and remote network control and status reporting. This processor-based subsystem interfaces with each fiber optic channel, with an orderwire communication link, and with external input/output devices and surveillance equipment. Three substantially autonomous processor-based sections which are dedicated to performing specific functions within the overall network operation are employed for carrying out these separate interfacing tasks. Each section of the processor-based subsystem in a terminal station contains its own CPU and associated memory and is programmed to carry out specific functions identified with that section. Each section is interconnected with the other two so that, internally, the subsystem is fully integrated.

Measures of the Effectiveness of Fault Signature Analysis

Abstract: A linear feedback shift register can be used to compress a serial stream of test result data. The compressed erroneous bit stream caused by a fault is said to form the "signature" of the fault. Since the bit stream is compressed, however, it is possible for an erroneous bit stream and the correct one to result in the same signature.

Sensor fault detection by activity monitoring

Abstract: Faults in a sensor (10) are detected by excess rate fault determination by taking the differentiated (58, 107), rate limited (60, 100, 111) integral (64, 112) from the raw sensor output (72, 113) and indicating a fault (15, 117) in the event that the difference exceeds a predetermined magnitude (76, 114). A null fault (22, 91) is provided in the event that the sensor output does not show a significant change (52, 88) within a given time interval (20, 80) whenever a related sensor (31) indicates (29, 84) that the first sensor (10) should have measurable activity. Both analog (FIG. 1) and digital (FIG. 2, FIG. 3) embodiments are disclosed.

Automatic fault detection and recovery system which provides stability and continuity of operation in an industrial multiprocessor control

Abstract: A multiprocessor computer control system for a process includes at least two central processors and respectively associated input/output systems. Control system faults are detected and a bootstrap microprocessor is triggered into its fault detector and recovery mode. The output control signals are placed on and central processors are stopped and restarted and then it is determined which if any of them is to be inoperative. A reconfigured control system is defined with the inoperative unit(s) excluded. The microprocessor switches the input/output systems as necessary to structure the control system in reconfigured form so that process control can resume without disturbance.

System-Level Fault Diagnosis

Abstract: Large multiprocessor networks require system-level fault diagnosis. Researchers have established and extended a model for such diagnosis.

Generalized Algorithms for Distribution Feeder Deployment and Sectionalizing

Abstract: Increasing effort is being focused on automated remote control of distribution feeder deployment and sectionalizing to improve service restoration time to unfaulted feeder sections and for transferring load between feeders. Digital processor algorithms which determine fault location and generate switching instructions automatically based on tree searching techniques utilizing switch tables that can be readily defined by an operator are described. Simulation results for fault location, fault isolation, and service restoration, including balancing between feeders using an illustrative simplified feeder configuration are shown.

Fault tolerant computational system and voter circuit

Abstract: A fault-tolerant computational system having a voter circuit which receives inputs from several computational devices and produces an output in agreement with a majority of the inputs. Also included is a clock circuit for synchronizing the output of data from the computational devices so that the input to the voter circuit is synchronized. The system may be adapted for fault detection by comparing the output of the voter circuit to the outputs of each of the computational channels.

Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration

Abstract: The construction of computer systems containing integrated circuit logic components with very large scale integration (VLSI), that is, many thousands of gates, is inevitable. Such levels of integration have already been achieved in memory components. There are significant problems in using some conventional fault-tolerant techniques in VLSI implementations for general purpose computers; consequently, modified approaches must be investigated.

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction

Abstract: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.

Distributed Fault-Tolerant Computer Systems

Abstract: Modular systems employing building-block VLSI circuits may provide fault tolerance to a variety of applications.

Multiple Fault Detection in Programmable Logic Arrays

Abstract: The increasing recognition of PLA's as efficient and viable modules for such purposes as microprogramming and design of sequential controllers has led to a growing interest in the development of optimum fault detection test sets for these modules. It is now well known that a fault type which is unique to PLA's is the class of contact faults. A single contact fault is the spurious presence or absence of a contact between a row and a column of a PLA. We consider in this paper the problem of determining the capability of complete single contact fault test sets to cover multiple contact faults of PLA's. Our approach consists of developing a model of PLA's which allows one to represent a contact fault in a PLA as a stuck-at fault in the model of the PLA. Using this model, it is shown that more than 98 percent of all multiple contact faults of size 8 and less are inherently covered by every complete single contact fault test set in a PLA. Applications of this model to stuck-at fault diagnosis are also discussed.

Sensor Fault Detection in a System with Random Disturbances

Abstract: Sensor faults are detected in an operating automatic system by a simplified version of the dedicated observer scheme Control inputs are augmented by a random disturbance of moderate intensity The dedicated observer in this case is a Kalman filter, driven by a single sensor This filter provides estimates of the outputs from the other, nonredundant, sensors A logical combination of these functionally redundant signals with the actual sensor signals provides prompt detection of incipient faults on all instruments without false alarms The scheme is applied to a simulation of the lateral axis control system of a hydrofoil boat in which four sensors are to be covered by the fault detection scheme Tests indicate that the scheme is robust with respect to variations in the intensity of the random disturbance

Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets

Abstract: The study of bridging faults (or short circuits that occur between conducting paths) has become increasingly important with the advent of LSI technology To date, only a very few papers have been published on this topic Specifically, little is known regarding undetectable bridging faults More importantly, what has yet to be explored are the effects of undetectable bridging faults on the tests designed to detect stuck-at faults

Multiprocessor information processing system having fault detection function based on periodic supervision of updated fault supervising codes

Abstract: A multiprocessor information processing system has an additional function to detect a fault occurring in a processor. A counter is provided for each of a plurality of processors for holding an associated fault supervising code. The code stored in the associated counter is periodically updated by the associated processor while the update status of the code is supervised on a cycle longer than the cycle of the updating period. If a fault occurs in one of the processors, the fault supervising code corresponding to that processor will not be updated. Thus, the faulty processor can be detected by periodically supervising the update status of the fault supervising code. The supervising operation can be carried out by software or hardware.

Bus fault detector

Abstract: The present invention comprises computer system equipment useful for detection of faults in data transmission within a computer system. Fault detection is accomplished by monitoring the current flow through a digital signal source means, which is characterized in that it only draws significant current during a non-transition period when a fault condition occurs.

Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection

Abstract: Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection.

Test Generation Techniques

Abstract: Existing test generation procedures are rooted in the SSI/MSI era. New techniques will cope with today's vastly more complicated LSI/VLSI systems.

Relevance of network theory to models of distributed/parallel processing☆

Abstract: This paper is concerned with the applicability of network theory to those aspects of distributed/parallel processing that can be modeled by marked graphs. First, several examples are given to illustrate that a wide variety of computation schemes can be modeled by marked graphs. Subsequently, the following topics are discussed: application of KVL to fault detection and isolation, KCL and Tellegen's Theorem applied to marked graphs, and the relationship between the maximum (minimum) storage requirement and the minimum (maximum) power.

Circuit for detecting faults in horizontal sync pulse signals

Abstract: To obtain a switching signal whenever a fault occurs in the synchronization signals of a video signal, a fault detection circuit has a counter which receives the signals to be tested at its clock input and reference signals at its control input. The reference signals have the same pulse frequency as the signals to be tested and are obtained from the signals to be tested by a change in keying ratio. The output of the counter is connected in its "clear" input and also, via a monostable flip-flop, to an input from an OR-gate. The other input of the OR-gate receives the reference signals via a diode and an RC-link. The desired switching signal is obtained at the output of the OR-gate.

Fault detection in a flame scanner

Abstract: A flame scanner has a sensing circuit (10) utilizing a photosensitive device (12) for monitoring and a logic circuit (20) which includes a flame detection circuit (22) and a fault detection circuit (24). The photosensitive device produces a current signal (13) indicative of the intensity of the flame. The current signal is fed to a logarithmic amplifier (14) and converted to a voltage signal (15). The voltage signal (15) powers an LED (18) with its output (4) impinging on the photosensitive device (12). The voltage signal (15) is also transmitted to the flame detection circuit and the fault detection circuit for simultaneous and independent processing. The flame detection circuit continuously processes the signal to determine if a stable flame is present, while the fault detection circuit continuously monitors the integrity of the photosensitive device and its associated sensing circuitry.

Signature monitoring of nuclear power plant dynamics - Stochastic modeling and case studies

Abstract: The increasing emphasis on the operational safety of nuclear power reactors necessitates the development of improved on-line and off-line monitoring methods during the normal plant operation. The random fluctuations in the neutron power and other system variables can be processed to extract information about sensor integrity, detection of anomalous conditions, estimation of stability margin, trend analysis, and incipient failure detection. This paper presents some of the recent developments in the areas of multivariate time series modeling and dynamic stochastic modeling with applications to both pressurized water reactors (PWRs) and boiling water reactors (BWRs). Three case studies - sensor fault detection using analytic redundancy, reactor diagnostics using multivariate spectral decomposition, and time dependent parameter estimation of BWR stability margin and steam velocity are discussed.

Flight experience with flight control redundancy management

Abstract: Flight experience with both current and advanced redundancy management schemes was gained in recent flight research programs using the F-8 digital fly by wire aircraft. The flight performance of fault detection, isolation, and reconfiguration (FDIR) methods for sensors, computers, and actuators is reviewed. Results of induced failures as well as of actual random failures are discussed. Deficiencies in modeling and implementation techniques are also discussed. The paper also presents comparison off multisensor tracking in smooth air, in turbulence, during large maneuvers, and during maneuvers typical of those of large commercial transport aircraft. The results of flight tests of an advanced analytic redundancy management algorithm are compared with the performance of a contemporary algorithm in terms of time to detection, false alarms, and missed alarms. The performance of computer redundancy management in both iron bird and flight tests is also presented.

MONITOR—An automatic bus location and communications system for Chicago

Abstract: Since 1970 the Chicago Transit Authority has had location-equipped vehicles in revenue service. Subsequently, the entire fleet, of over 2400 vehicles has been equipped with two-way voice/data radios with the location feature. Since the initial 1970 Demonstration, the location technique of "broad-field proximity" (high-band VHF signposts) has been utilized, to provide location information. This paper will describe the system configuration and operation, including design criteria such as RF coverage areas, channel assignments and loading, and computer polling rates for location and automatic correlation data (bus number versus Garage/Run number). Emphasis will be placed upon the dual computer system (host front-end) which includes: system monitoring by central dispatchers; emergency alarm (with location) monitoring and reporting; mobile mechanical irregularity monitoring and reporting (equipment fault isolation - through mobile unit diagnostics); MIS capability; and future AVM function monitoring and reporting (start run indicators on board the vehicles, passenger counter, and odometer data acquisition). System reliability and availability levels experienced, as well as maintenance procedures utilized will be outlined. System expansion capabilities, and flexibility will be described, including the incorporation of routine bus transfers between garages, and the addition/deletion of vehicles in the system.

Automatic switching system of dual-processor system

Abstract: PURPOSE:To facilitate the processing of a switching controller by detecting a fault of a processor by monitoring the states of two timers, by providing the switching controller with two timers which are set at constant intervals of time by two processors and generate fault detection signals when not set. CONSTITUTION:The bus switching gate 42 is connected to two processors through internal buses 37 and 38, and consequently the internal buses 37 and 38 are switched and connected to an external bus 39. Those buses 37 and 38 are provided with timers T1 and T2 which are set at constant intervals of time by the processors and supply fault signals to a monitoring device 41 when not set. This monitoring device 41 monitors signals from the timers T1 and T2 and, when detecting a fault of a processor, controls the switching gate 42 to change connections between the internal buses 37 and 38, and external bus 38, thus simplifying the processing of the switching controller.

Fault detection system

Abstract: PURPOSE:To secure a quick information of the fault occurrence to the maintainer and thus to increase the stability and the working efficiency for the system by providing the means which decides the processor faulty in case the frequency of the information delivered from the processor is under the prescribed level. CONSTITUTION:Processor CCP carries out the process to go to see the cue of peripheral control unit PCP. Accordingly, CCP always gives the order to PCP with over a fixed frequency even when no traffic is applied at all as long as CCP has no fault. CCP fault detection circuit FDC checks whether or not the order is given to PCP with a fixed frequency or more as to each CCP. And such CCP that features less frequency than the fixed level for the order to be given to PCP is decided faulty. This fault is informed to system control processor MCP, and thus MCP decides which CCP has the fault to give the off-line to the faulty CCP as well as to inform the faulty CCP to the maintainer.

Microcomputer-based real-time/online f.f.t. processor

Abstract: The fast Fourier transform (fft) has found wide applications in areas requiring the processing of uniformly sampled signals This paper investigates the characteristics of using a standard, inexpensive micro-computer system to implement an fft processor operating in either real-time or online mode Various aspects on the maximum sampling rate in either mode of operation, such as the limitation by the system input/output time and fft computation time, as well as the aliasing-free condition to process bandlimited periodic signals, are revealed The sampling clock is made adaptive to the real-time signal So the processor is capable of processing signals from dc up to the online aliasing frequency An example of real-time/online line-voltage fault detection is also included

Plant data record retrieving device at fault occurring time

Abstract: PURPOSE:To secure the quick and accurate investigation to the cause of the fault by carrying out the plant data recording and display of the fault occurring time in parallel to the plant data retrieving, reproduction and display of the past examples. CONSTITUTION:Fault detection signal 10 generated at plant 1 is supplied to trigger contents deciding unit 2 in the form of the trigger signal. Recording data selector 3 selects plant data 13 among full plant data 12 based on trigger signal contents data 11 given from unit 2 trigger-related plant corresponding table 4 memorized previously and then sends the data to data recorder 5. Recorder 5 is replaced with another one when the capacity becomes full, and old cassette 201 is stored in plant data library 20 of the fault occuring time. Controller 8 retrieves the past example corresponding to data 11 out of lists of library 20, and then displays the cassette No. and the recording case No. on CRT display unit 7. After this, cassette 202 is loaded to recording data reproducer 6. And signal 18 is transmitted after confirmation, and the trend of plant data 15 of fault occurring time is displayed on unit 7. Then controller 8 transmits signal 17 to recorder 5 to secure display of the present faulty data.

Fault detection in integrated circuit chips and in circuit cards and systems including such chips

Abstract: VLSI chips contain a very high density of logic elements and have only a limited number of pin connections making complete testing by conventional means impracticable. The invention provides a self-verifying chip. The chip includes a data processing chain (10) and a plurality of fault detecting circuits (13,14,15) coupled to the data processing chain. A plurality of internal stimulus generators (18,19,20) generate test signal patterns in response to a supervisory control (21) which are applied to intermediate points of the data processing chain. Outputs from the fault detecting circuits (13,14,15) are applied to an error status generator (16) which provides error signals indicating fault conditions at various points of the data processing chain. Fault detecting circuits (18A.21A) may also monitor the internal stimulus generators and the supervisory control means. The devices of the data processing chain may normally operate in a parallel-load mode, but may be loaded with the test signal patterns in serial mode. The chip may include duplicate functional or complementary logic for the data processing chain, and the fault detecting circuits may be arranged to check the operation of the two logic chains against each other. A number of chips according to the invention may be mounted on a card, with a card fault detector receiving the outputs of the error status generators of the chips and providing an output indicating the faults detected in the chips and in the card wiring, and, in turn, in a complete system the outputs of the card fault detectors may be applied to a system fault generator monitoring the occurrence of faults in the whole system.