Showing papers on "Fault detection and isolation published in 1985"

Fault diagnosis of analog circuits

Abstract: In this paper, various fault location techniques in analog networks are described and compared. The emphasis is on the more recent developments in the subject. Four main approaches for fault location are addressed, examined, and illustrated using simple network examples. In particular, we consider the fault dictionary approach, the parameter identification approach, the fault verification approach, and the approximation approach. Theory and algorithms that are associated with these approaches are reviewed and problems of their practical application are identified. Associated with the fault dictionary approach we consider fault dictionary construction techniques, methods of optimum measurement selection, different fault isolation criteria, and efficient fault simulation techniques. Parameter identification techniques that either utilize linear or nonlinear systems of equations to identify all network elements are examined very thoroughly. Under fault verification techniques we discuss node-fault diagnosis, branch-fault diagnosis, subnetwork testability conditions as well as combinatorial techniques, the failure bound technique, and the network decomposition technique. For the approximation approach we consider probabilistic methods and optimization-based methods. The artificial intelligence technique and the different measures of testability are also considered. The main features of the techniques considered are summarized in a comparative table. An extensive, but not exhaustive, bibliography is provided.

Statistical Fault Analysis

Abstract: Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This method defines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-free simulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation. The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes.

PROTEST: A Tool for Probabilistic Testability Analysis

Abstract: The CAD-tool PROTEST (Probabilistic Testability Analysis) is presented PROTEST estimates for each fault of a combinational circuit its detection probability which can be used as a testability measure Moreover it calculates the number of random test patterns which must be generated in order to achieve the required fault coverage It is also demonstrated that the fault coverage will increase and the necessary number of random patterns will drastically decrease, if each primary input is stimulated by test patterns having specific probabilities of being logical "1" PROTEST uses this fact and determines for each input the optimal signal probability for a randomly generated pattern

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults

Abstract: In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.

Status of High Impedance Fault Detection

Abstract: This paper presents the issues associated with the detection and clearing of high impedance faults on distribution feeders. High impedance faults are those faults with current too low to be reliably cleared by conventional overcurrent protection. These faults commonly occur as fallen conductor faults and pose a hazard to the public. The status of research on this subject is reviewed, and possible improvements are evaluated. The several complex technical, legal, economic and operational problems involved in high impedance fault detection are discussed. A complete solution to the high impedance fault problem does not exist at this time, but it is important that utilities take steps to address the problem.

Engine Fault Analysis: Part II---Parameter Estimation Approach

Abstract: The general fault analysis problem can be divided into two parts: fault detection and diagnosis (location). Fourier series, autocorrelation, and other techniques have been used for fault detection. However, these approaches cannot be utilized for locating the faults. In this paper a methodology is presented to locate faulty cylinder(s). The procedure involves the development of a mathematical model of the engine dynamics. This model takes into consideration the cylinder gas pressure, engine inertia, and load. The resultant torque is computed by using parameter estimation techniques. The parameter estimation technique employed can determine time-varying parameters without prior knowledge of the structure of the parameter. In the problem at hand, this is an important requirement. The resultant torque is the net of the cylinder gas torque and the frictional torque. The model and the estimation procedure have been verified by performing tests on a single-cylinder engine. A discriminant function has been defined to classify the performance of each cylinder. Our results indicate that the amplitude of the resultant torque can be used to identify the faulty cylinder(s). We have verified this approach by tests and studies on a six-cylinder engine. In our experiments we have studied cases involving one or two faulty cylinders.

Concurrent Fault Detection in Microprogrammed Control Units

Abstract: This paper specifies procedures for defining a monitor circuit that can detect faults in microprogram sequencers. The monitor and the sequencer operate in parallel and errors are detected by comparing outputs from the monitor circuit with outputs from the sequencer. Faults that cause errors in the flow of control are detectable, as well as some faults that cause errors only in the microinstruction fields. The design procedure presented for monitors consists of four parts. First, a model of the program flow is constructed that only retains the information required to define a monitor. Second, faults in a specified fault set are modeled by the errors they cause in the program flow model. Third, the functional requirements of the monitor are specified in terms of partitions on the states of the program flow model. Fourth, the logic design of the monitor is completed.

Augmented Models for Statistical Fault Isolation in Complex Dynamic Systems

Abstract: The equation error approach to fault isolation implies the statistical testing of balance equation errors. In this paper, some substantial extensions to the existing methodology are proposed, including - generalized linear dynamic models - the concept of statistical isolability - the idea of and an algorithm for model augmenting - fault sensitivity analysis and filtering

Engine Fault Analysis: Part I-Statistical Methods

Abstract: Several studies have been performed to detect faults in engines. Fourier series and autocorrelation-based methods have been shown to be useful for this purpose. However, these and other methods discussed in the literature cannot locate the fault. In this paper, the focus is on techniques that will enable the location of the fault. In general, our approach involves the analysis of the instantaneous angular velocity of the flywheel. Three methods of analysis are presented. The first method depends on the computation of a set of statistical correlations. The second method is based on evaluation of similarity measures. These methods are able to locate faults in several tests that have been performed. The third approach uses pattern recognition methods and involves three stages?data extraction, functional approximation to determine a feature vector, and classification based on a Bayesian approach. This method is computationally more complex than the other approaches. However, on the basis of the experimental results it appears that the third method leads to a lower error rate. Cases involving faults in one and two cylinders are presented.

Programmable integrated circuit fault detection apparatus

Abstract: An integrated circuit fault detection system. The integrated circuit fault detection system includes gate means associated with each functional input and functional output of the chip. The gate means are connected between the functional input and functional output terminals and the bonding pad and are controllable to allow the chip to operate in normal fashion using the input and output terminals thereof and the bonding pads associated therewith. The gate means are also controllable to read test data into a functional input terminal of the chip, write test data out of the functional output terminal of the chip, drive test data from chip functional circuitry through the bonding pad off chip, and accept test data from the outside world through a bonding pad and transfer the test data to chip functional circuitry. The test results can then be analyzed to determine if the chip is functioning properly.

Analyzing safety and fault tolerance using time Petri nets

Abstract: The application of Time Petri net modelling and analysis techniques to safety-critical real-time systems is explored and procedures described which allow analysis of safety, recoverability, and faulttolerance. These procedures can be used to help determine software requirements, to guide the use of fault detection and recovery procedures, to determine conditions which require immediate mitigating action to prevent accidents, etc. Thus it is possible to establish important properties during the synthesis of the system and software design instead of using guesswork and costly a posteriori analysis.

A Comparison of Measured High Impedance Fault Data to Digital Computer Modeling Results

Abstract: Staged fault tests were-cohducted by Pennsylvania Power and Light Company to verify the performance of the Ratio Ground Relay concept. Previous development and tasting efforts, regarding this relay have been reported (1, 2). This paper presents the field measured fault current data in entirety and compares the field. data with SCADA collected data and digital computer data. The paper documents that a 12-kV four-wire multi-grounded neutral distribution feeder can be accurately modeled on a. digital computer, and that the computer results are field verifiable. The favorable results of this comparison provide confidence in the modeling method for use in development, testing, and application of new relay methods.

Development and Field-data Evaluation of Single-end Fault Locator for Two-Terminal HVDC Transmission Lines, Part I: Data Collection System and Field Data

Abstract: A prototype data collection system was developed in order to acquire field data as a part of the development of HVDC fault location techniques. The system was installed at the Celilo Converter Station of the Pacific HVDC Intertie, owned by the U. S. Department of Energy-Bonneville Power Administration in May, 1983. It monitors two line voltages, one neutral voltage, and two line currents. It also has an event detection function to trigger saving data onto a diskette. In this paper (Part I) the data collection system hardware is described, and several field data are plotted and analyzed. Development of an HVDC fault location algorithm and its evaluation using field data are given in the second paper, Part II.

A fault detection and isolation method applied to liquid oxygen loading for the space Shuttle

Abstract: Process-monitoring and fault location techniques have been developed at the Kennedy Space Center in a domain of mixed media control in NASA's Space Shuttle Launch Processing System. An intuitively appealing diagnostic technique and representation of the system's structure and function were formulated in cooperation with system engineers. Functional relationships that determine the consistency of sensor measurements are represented by symbolic expressions embedded in frames. Functional relationships are stored in exactly one place, so they must be inverted to determine hypothetical values for possibly faulty objects. Propagating these hypothetical states to other sensors permits the location of faults. Standard symbolic inversion techniques have been extended to include conditional functions. A demonstration system is operating, and its evaluation will soon use live data from the firing rooms at KSC.

Digraph Matrix Analysis

Abstract: This paper describes a systematic procedure for constructing a Boolean reliability model from plant schematics, and a technique for determining all sets of single and double component failures which will cause system failure. This technique, called digraph matrix analysis, uses a fault graph instead of the more traditional fault tree. Digraph matrix analysis was recently applied to the system interaction analysis of a very large safety system (over ten thousand components) and is being used to determine security system vulnerabilities.

Fault Tolerant Computer System for the A129 Helicopter

Abstract: The A129 integrated multiplex system (IMS) is a highly reliable computer system designed to implement automatic flight control, navigation, system monitoring, and other flight-critical and mission related tasks. The reliability of the IMS has been achieved through the development of hardware-implemented and software implemented fault-tolerance techniques which exploit several unique architectural and hardware characteristics. This paper describes the fault-tolerance design philosophy, the IMS architecture, the fault detection and fault recovery techniques, and the hardware and software structures. Also presented is a Markov reliability analysis which was used to quantify the reliability of the system.

Feeder Protection and Monitoring System, Part II: Staged Fault Test Demonstration

Abstract: This paper describes the demonstration of three Texas A&M University experimental Feeder Protection and Monitoring Systems during staged fault tests at Houston Lighting and Power and at Public Service Company of New Mexico. The purpose of the experimental devices is to demonstrate improvements in the protection and monitoring capabilities of distribution relays. The Feeder Protection and Monitoring System is a microcomputer-based device installed at a distribution substation which includes arcing fault detection and overcurrent relaying. The arcing fault detector identifies many ground faults which exhibit current too low to be picked up by overcurrent devices. The digital overcurrent relay provides several enhancements over electromechanical relays. The system also demonstrates some of the advantages of computer automation of distribution protective devices by providing remote monitoring, data retrieval and adjustment of settings. These features of the Feeder Protection and Monitoring System were demonstrated during the staged fault tests. The paper includes plotted data and logs of the system performance during the fault tests.

The S-Algorithm: A Promising Solution for Systematic Functional Test Generation

Abstract: We present a new algorithm for functional test generation of VLSI systems. This algorithm for functional test generation for each testable register-transfer (RT) level fault defined in our established fault model. The technique developed is appropriate for test generation in top-down Computer-Aided Design process. The development of the algorithm is based on two foundations: the RT-level fault model and symbolic execution technique. A well-defined RT-language for the functional representation of a digital system is described. Based on this language, the RT-level fault modeling and fault collapsing analysis are performed. The fault model is established to lay an analytical foundation for the investigation of faulty behavior among RT-level fault types. The RT-level symbolic execution technique is used to derive test patterns during test generation. Major problem areas are defined and appropriate solutions are presented. The whole test generation process is divided into three stages: preprocess, the S-algorithm, and post-process. "Divide and conquer" principle is used throughout the test generation process for systematic problem solving. The S-algorithm is the heart of the overall algorithm. It performs test pattern generation based on the reduced fault model using machine symbolic execution. This test generation algorithm has been implemented in PASCAL on IBM 370/168.

Determination of optimal measuring sites for fault detection of non-linear systems

Abstract: This paper describes how to determine the optimal set of measuring sites for identifying faults that can be detected if full information about the state variables can be obtained. We present here a new reduced-order time-varying linear observation technique to estimate the state variables in non-linear systems with unknown system parameters. We present a strategy to employ this observation technique to determine an optimal set of measuring sites from among an excess number of sites in the sense of minimizing the measuring cost for fault detection. We also develop a new theoretical result for state observation of non-linear systems with unknown parameters and, for an example application, demonstrate via simulations how to determine the optimal measuring sites and how to detect faults in a non-linear electrical machine.

Feeder Protection and Monitoring System, Part I: Design, Implementation and Testing

Abstract: This paper describes the development of a microcomputer-based Feeder Protection and Monitoring System at Texas A&M University. The Feeder Protection and Monitoring System includes an overcurrent relay to provide overcurrent protection for a distribution feeder and it includes an arcing fault detector which identifies some low current faults which are not cleared by overcurrent protection. The system also provides a monitoring capability which supports data storage and remote interaction with a user. The paper describes the design of the system, how the design was implemented, and the testing of three prototypes which were built for research purposes. These units properly demonstrated the overcurrent protection, arcing fault detection and monitoring functions of the system, as well as many of the features of power system automation.

CUSP: A 2-/spl mu/m CMOS Digital Signal Processor

Abstract: This paper describes the Cornell University Signal Processor (CUSP), a 60 000 transistor 2-/spl mu/m CMOS processor custom designed to compute the Fast Fourier Transform (FFT) and related algorithms. Operating on a 50-MHz clock, the bit-serial arithmetic hardware on a CUSP chip performs over 15 million 20 X 20 bit multiplications per second and computes a 1024 point FFT in 1.33 ms. The chip architecture is presented along with a description of the arithmetic, control, and fault detection circuitry. The inclusion of these components on a single chip is shown to allow large fault tolerant arrays of CUSP processors to be efficiently employed for high-performance applications.

Television power supply turn-on protection circuit

Abstract: A power supply for a television deflection apparatus is turned-on by a user initiated turn-on command. A fault detection circuit samples a voltage derived from the deflection circuit at the end of a predetermined interval that follows the turn-on command. The fault detection circuit issues a turn-off command to immediately shutdown the power supply, if such voltage is below a predetermined level indicative of a fault condition.

Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays

Abstract: The increasing number of applications of programmable logic arrays (PLA's) has evoked the development of test generation methods for these circuits. There are known methods for complete single contact fault detection test set generation. These test sets fail to detect all multiple faults in a PLA due to the phenomenon of masking. In this correspondence, we present a method to quantitively predict the multiple fault coverage capability of a single fault detection test set in a PLA. The method enables us to determine the coverage ratio, which is defined as the ratio of the number of multiple contact faults detected by a single fault test T c to the total number of all multiple faults. It is shown that the multiple fault coverage ratio of T c drops with an increasing size of faults, and most unexpectedly, the ratio increases with an increasing number of rows. The number of crosspoints in one product line has very little influence on the ratio.

Generating system with fault detection

Abstract: "Doorbelling" in a generating system including a fault detecting circuit is prevented without the use of auxiliary power supply for a generator control unit. The generating system includes a permanent magnet generator (14) driving an exciter winding (18) and a relay (26) is utilized for interconnecting the two. Control of the relay (26) is exercised by a microcomputer (32) including a non-volatile memory (48) and programmed to remember the occurrence of a fault and thereafter prevent the relay (26) from cyclically opening and closing in response to power changes occurring as a result of connection and disconnection of the exciter winding (18) from the permanent magnet generator (14).