Showing papers on "Fault detection and isolation published in 1986"

Fault and error models for VLSI

Abstract: This paper describes a variety of fault and error models which are used as the basis for designing fault-tolerant Very Large Scale Integrated (VLSI) systems. The fault models describe physical defects and failures and the input patterns which will expose them, and are suitable for testing, while error models describe the effects on the functional outputs of defects and are useful for on-line error detection. The models are described at various levels of abstraction. The differences between fault and error models for identical functional modules are also illustrated.

The hybrid automated reliability predictor

Abstract: In this paper, we present an overview of the hybrid automated reliability predictor (HARP), under development at Duke and Clemson Universities. The HARP approach to reliability prediction is characterized by a decomposition of the overall model into distinct fault-occurrence/repair and fault /error-handling submodels. The faultoccurrence/repair model can be cast as either a fault tree or as a Markov chain and is solved analytically. Both exponential and Weibull time to failure distributions are allowed. There are a variety of choices available for the specification of the fault/error-handling behavior that may be solved analytically or simulated. Both graphical and textual interfaces are provided to HARP.

Computer assisted vehicle service featuring signature analysis and artificial intelligence

Abstract: A computer based technician terminal is connected to a vehicle being serviced using an assembly line data link (ALDL) connection from an on-board computer. The data link provides status information and fault codes. The technician is led through various procedures. During set up, the technician connects an ALDL cable from the terminal to the vehicle, the vehicle indentification number (VIN) is entered and vehicle options are identified. A fault detection procedure (FDP) in the terminal detects vehicle malfunctions by interrogating data received (via the ALDL) from the on-board computer. A fault analysis procedure (FAP), using the fault codes from a table as arguments, does a sequential compare against the contents of a fault analysis table containing fault codes. In a fault sequencing procedure (FSP), for each fault code passed by the FAP, there is a list containing the name(s) of one or more isolation procedures. A fault isolation procedure (FIP) is provided for electrical or electronic components on the vehicle to perform a complete test of the related part using a multifunction test probe. Fault repair procedures guide the technician through the proper steps to accomplish the repair, replacement or adjustment required.

Survey of Expert Systems for Fault Detection, Test Generation, and Maintenance

Abstract: The use of knowledge engineering in diagnostic systems, is aimed primarily at exploiting procedural knowledge (about: systems operations, configuration, observations, calibration, maintenance), in connection with failure detection and test generation tasks. Next, the goal is to devise knowledge representation schemes whereby the failure events can be analyzed by merging highly diverse sources of information: analog/digital signals, logical variables and test outcomes, text from verbal reports, and inspection images. The final goal is to ease the operator workload when interfacing with the system under test and/or the test equipment, or with reliability assessment software packages. The paper will present key notions, methods and tools from: knowledge representation, inference procedures, pattern analysis. This will be illustrated by reference to a number of current and potential applications for e.g.: electronics failure detection, control systems testing, analysis of intermittent failures, false alarm reduction, test generation, maintenance trainers.

Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems

Abstract: An important consideration in the design of high- performance multiple processor systems should be in ensuring the correctness of results computed by such complex systems which are extremely prone to transient and intermittent failures. The detection and location of faults and errors concurrently with normal system operation can be achieved through the application of appropriate on-line checks on the results of the computations. This is the domain of algorithm-based fault tolerance, which deals with low-cost system-level fault-tolerance techniques to produce reliable computations in multiple processor systems, by tailoring the fault-tolerance techniques toward specific algorithms. This paper presents a graph-theoretic model for determining upper and lower bounds on the number of checks needed for achieving concurrent fault detection and location. The objective is to estimate ate the overhead in time and the number of processors required for such a scheme. Faults in processors, errors in the data, and checks on the data to detect and locate errors are represented as a tripartite graph. Bounds on the time and processor overhead are obtained by considering a series of subproblems. First, using some crude concepts for t-fault detection and t-fault location, bounds on the maximum size of the error patterns that can arise from such fault patterns are obtained. Using these results, bounds are derived on the number of checks required for error detection and location. Some numerical results are derived from a linear programming formulation.

Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops

Abstract: The authors present evidence that conventional tests cannot detect FET stuck-open faults in several CMOS latches and flip-flops Examples are given to show that stuck-open faults can change static latches and flip-flops into dynamic devices?a danger to circuits whose operation requires static memory, since undetected FET stuck-open faults can cause malfunctions Designs are given for several memory devices in which all single FET stuck-open faults are detectable These memory devices include common latches, master-slave flip-flops, and scan-path flip-flops that can be used in applications requiring static memory elements whose operation can be reliably ascertained through conventional fault testing methods

On Fault Isolation and Identification in t 1 /t 1 -Diagnosable Systems

Abstract: Consider a classical PMC system composed of n units [1] where it is assumed that at most t1 of these units are faulty. Such a system is said to be t1/t1-diagnosable [3] if, given any complete collection of test results, the set of faulty units can be isolated to within a set of at most t1 units. This paper exposes some new, important properties of general t1/t1-diagnosable systems to present an O(n2.5) algorithm by which all the faulty units except at most one can be correctly identified and all the faulty units can be isolated to within a set of t1 or fewer units in which at most one can possibly be fault free.

Fault detection circuit

Abstract: In a solenoid fuel injection system, an output transistor (16) receives switching signals to control through current therein which is provided to a solenoid fuel injection coil (11) in series with a current sensing resistor (17). A current control circuit (12) provides pulse width modulation control of solenoid current by monitoring the voltage across the sensing resistor. The fault detection circuit provides separate fault signals for short circuits at either the first or second end terminals (E, H) of the solenoid coil. Separate voltage comparators (18, 23) monitor voltages at the first and second end terminals, and separate delay timers (20, 25) effectively gate the comparator outputs to indicate actual detected short circuits. Each of the fault detection signals sets a fault latch (22) which then acts to reduce current through the output transistor and coil. The fault latch is periodically reset. For a fault detection, the output transistor is protected from excessive current resulting from a short circuit at one end terminal (H). The transistor and coil are also protected from a short circuit at the other end terminal (E) which results in the lack of a current sense signal causing the controller (12) to attempt to maintain the output transistor constantly on.

A Multi-Microprocessor Based Travelling Wave Relay - Theory and Realization

Abstract: A new travelling wave digital protection scheme to be used as an ultra high speed (UHS) EHV/ UHV transmission line relay is presented in this paper. Some of the potential problems and limitations associated with other travelling wave schemes are avoided. Verification of the relay operating principles is presented through digital computer numerical simulation using an electromagnetic transients program (EMTP) in conjunction with simulation of the proposed algorithm. Parallel digital processing is incorporated through multi-microprocessor implementation. Hardware and software of a multiprocessor prototype are managed in a way to fit the algorithm requirements in as simple a construction as possible. The resulting scheme achieves significantly improved security and dependability, in addition to the main features: fault classification and UHS phase selection in selective-pole schemes with minimum communication between the protected ends.

A Microprocessor-Based Technique for Detection of High Impedance Faults

Abstract: Detection of high impedance faults on distribution systems is difficult due to the low current levels which flow in the fault. The objective is to detect these faults with some device or mechanism situated at the substation without modification to the distribution lines themselves. The technique presented in this paper monitors the unbalance in the fundamental, third and fifth harmonic feeder currents at the substation and performs a statistical evaluation of the present unbalance relative to past levels of unbalance. Using hypothesis testing, if the level of unbalance exceeds a threshold, a fault is indicated. The technique enploys a real-time algorithm suitable for implementation on a microprocessor-based digital relay located in the substation.

Method for controlling AMT system including gear neutral sensor signal fault detection and tolerance

Abstract: A method for controlling an AMT system (10) is provided including sensing and identifying faulty input signals (GNS) from the gear neutral--not gear neutral sensor (76), and, if the signal is faulty, modifying the logic method for control (42) to a logic method tolerant of the identified faulty input signal.

Experiments in software reliability: Life-critical applications

Abstract: Digital computers are being used more frequently for process control applications in which the cost of system failure is high. Consideration of the potentially life-threatening risk, resulting from the high degree of functionality being ascribed to the software components of these systems, has stimulated the recommendation of various designs for tolerating software faults. The author discusses four reliability data gathering experiments which were conducted using a small sample of programs for two problems having ultrareliability requirements: n-version programming for fault detection, and repetitive run modeling for failure and fault rate estimation. The experimental results agree with those of M. Nagel and J.A. Skrivan (1982) in that the program error rates suggest an approximate log-linear pattern and the individual faults occurred with significantly different error rates.

Method and apparatus for isolating faults in a digital logic circuit

Abstract: The method and apparatus for isolating faults in circuitry of a digital computer includes the use of a fault isolation generation program which provides a data base containing a list of possible faulty components for each cycle of the computer's clock for execution by a service processor of the actual computer during testing. The fault isolation generation program is generated by using a simulator loaded with a mathematical model of the actual computer in connection with the execution of the diagnostic program executed on the actual computer during testing. The fault isolation program generates a list of circuit elements capable of generating fault indications, excluding circuit elements not capable of generating such fault indications.

Roving Emulation as a Fault Detection Mechanism

Abstract: In this paper we present a new built-in test methodology for detecting and locating faults in digital systems. The technique is called roving emulation and consists of an off-line snap shot type emulation or simulation of operating components in a system. Its primary application is in testing systems in the field where real-time fault detection is not required. The primary performance measure of this test schema is taken to be the expected value of the error latency, i.e., the time required to detect a fault once it first occurs. The primary results of this paper deal with deriving equations for the error latency. We present both a probabilistic and service-waiting model to analyze the expected error latency in a system tested via roving emulation. The effects of various controllable and uncontrollable system parameters on error latency are studied. Finally, the technique is applied to a system consisting of combinational logic modules, and numerical results are presented.

Fault detection in programmable logic arrays

Abstract: When designing fault-tolerant systems including programmable logic arrays (PLAs), the various aspects of these circuits concerning fault diagnosis have to be taken into account. The peculiarity of these aspects, ranging from fault models to test generation algorithms and to self-checking structures, is due to the regularity of PLAs. The fault model generally accepted for PLAs is the crosspoint defect; it is employed by dedicated test generation algorithms, based on the fact that PLAs implement a two-level combinational function. The problem of accessing inputs and outputs of the PLA can be alleviated by augmenting the PLA itself so as to simplify the test vectors to be applied, making them function independent in the limit. A further step consists in the addition of the circuitry required to generate test vectors and to evaluate the answer, thus obtaining a built-in self-test (BIST) architecture. Finally, high reliability can be achieved with PLAs featuring concurrent error detection.

Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams

Abstract: This correspondence presents a test generation methodology for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers, adders, RAM's, and MUX's. The functions of the individual modules are described using binary decision diagrams. A functional fault model is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.

Checkpoint Faults are not Sufficient Target Faults for Test Generation

Abstract: Stuck-at faults on primary inputs and fan-out branches are commonly used as target faults in test generation algorithms for combinational circuits. This correspondence shows that these faults may not constitute an adequate set of target faults. A procedure is presented for selecting a set of target faults with the property that the detection of all detectable faults from this set guarantees the detection of all detectable faults in the circuit.

Method of and apparatus for fault detection in digital circuits by comparison of test signals applied to a test circuit and a faultless reference circuit

Abstract: A fault detection system for electronic circuits is disclosed which comprises a detection circuit in which the crosscorrelation values between the test signal sequence, input to a circuit to be tested, and the output signal sequence from it, with no delay and with delays made in steps to a predetermined time interveral either in the test input signal or in the output sequence, are counted, a reference circuit in which the crosscorrelation values between the test signal sequence input to a faultless reference circuit and the output signal sequence from it, are counted, and a comparator for comparing the crosscorrelation values from both the detection and reference circuit In one preferred embodiment, one or more of the conventional data compression methods selected from the group of the one's counting, transistion counting, auto-correlation, and C R C methods are incorporated for operation in conjunction with the system

Method and an apparatus for marking faults on rapidly moving material webs

Abstract: In a method of marking faults on rapidly moving material webs the material web is moved past a fault detection scanning device, which cyclically scans the web transverse to its longitudinal direction, and past a marking device at a defined distance therefrom. Signals coming from the fault detection scanning device (16) are analyzed one after the other to determine whether they are fault signals or structure signals. The fault signals which are detected are stored with their web coordinates. Checks are made at short time intervals as to whether a fault signal is present in the store (11) which corresponds to the longitudinal coordinate which is just moving past the marking device (13). A marking is effected if a fault signal is present at the corresponding web coordinates (FIG. 1).

Fault detection device for thermal printing head heating circuits

Abstract: A thermal printer with a fault detection circuit for detecting faults in heating elements used in the printer includes a print head containing the heating elements and a heating circuit associated with each element, a power supply, and a switching circuit interposed between the power supply and the print head. The fault detection circuit includes a current supply circuit, preferably a constant current source, which is connected in parallel to the switching circuit. A control circuit selects either a normal printing mode or a print head fault detection mode. In the fault detection mode, the switching circuit is disabled enabling the fault detection circuit to pass a test current through each of the heating elements for detecting any faults therein.

FAUST: An MOS Fault Simulator with Timing Information

Abstract: This paper describes FAUST, an MOS fault simulator with timing information. FAUST simulates the effects of realistic physical failures on MOS circuits and uses a static concurrent fault-simulation technique to evaluate the fault-free circuit and all the faulty circuits in one pass. FAUST produces voltage waveforms as well as logic tables with delay information for the fault-free circuit and for each of the faulty circuits.

Fault detection circuit for a thermal print head

Abstract: A thermal printer with a fault detection circuit for detecting faults in heating elements of the printer includes a print head containing heating elements and a heating circuit for each heating element and a power supply for supplying power to the heating elements. Power is supplied to the print head either directly through one terminal of the power supply or indirectly, during a test mode, through a fault detection circuit which is also connected to the print head. The fault detection circuit includes a constant voltage source, preferably formed of series-connected diodes, through which power flows to the print head. Current passing through the constant voltage source activates a photocoupler having an output the voltage of which determines whether a current is or is not flowing into the print head. A CPU which controls overall operations in the printer monitors the photocoupler and selects either a normal printing mode or a print head test mode. In the test mode, the CPU enables sequentially each of the heating circuits to determine their functional integrity.

On-line, limited mode, built-in fault detection/isolation system for state machines and combinational logic

Abstract: A mechanism for the testing of digital signal processing circuitry (state machines and combinational logic) is built-in and continuously on-line with the system being tested. The operation of the signal processing architecture is monitored dynamically, namely across state transitions, employing a parity prediction operator which predicts the parity that should be produced by combining the contents of selected inputs and outputs of the architecture prior to and subsequent to a signal processing transition. If, due to a single bit failure, the predicted parity is not achieved, the output of an error detector will indicate a state other than that corresponding to the predicted parity and thereby report an error. To ensure accurate operation of the error reporting mechanism, the error signal is modulated by a clock signal the frequency of which is relatively low compared with the system clock that controls state transitions. The detection of interconnect wiring faults (e.g. among state machines) is accomplished by executing an exclusive-OR modulation of the digital signals with a prescribed clock signal the frequency of which is lower than the highest signal level transition rate expected on a communication link upstream of transmission over the link whose continuity is being tested. At the downstream end of the link, immediately adjacent entry into the state machine, the link is coupled to an activity detector. If the activity detector fails to detect change of state activity (i.e. the modulating clock) during a prescribed time window, a fault on the link is declared.

A Delay Test System for High Speed Logic LSI's

Abstract: This paper presents a delay test system which detects the delay faults located in LSI chips. Fault model and the measure of fault coverage are defined. This system features easy to use operation for providing the test data, including fail safe design to violation of scan design rule, quick turn around time for test data generation, and consideration for delay fault analysis. The delay test is applied to the LSIs for M-68X series computers and justified its effectiveness to assure computer system's maximum performance.

On the design of fault-tolerant signal detectors

Abstract: In this paper we analyze the effects of hardware faults on the performance of computer-implemented signal detectors, as measured by the probability of detection and the probability of false alarm. We then use these results to design fault-tolerant detectors using hard-ware redundancy.

Apparatus and method for detecting time-related faults

Abstract: On-line timing signal fault detection by taking advantage of differential signal distribution commonly employed in digital data processing systems. An acceptance window indicative of permissible phase shift variations between the differential signals is established using a plurality of flip-flops having clock and data inputs to which delayed, undelayed, inverted and uninverted versions of the differential signals are applied in a predetermined manner. Also included is the capability of providing fault detection even when one of the differential signals is lost.

Spectral Signature Testing of Multiple Stuck-at Faults in Irredundant Combinational Networks

Abstract: Earlier spectral signature testing methods are extended to the multiple stuck-at fault model. The testability condition for multiple- input faults is established and a minimal spanning signature (MSS) is defined to cover all these faults. It is then shown that an MSS, which in most cases contains a single spectral coefficient, will detect over 99 percent of all input and internal multiple faults. An approach is described to obtain a complete signature for all multiple faults in any irredundant combinational network with comparatively small numbers of fan-outs. Tree networks that include XOR/XNOR gates are shown to be easily tested. Internally fan-out-free and general irredundant networks are also considered. A design approach is proposed to enable a network to be tested for all single and most multiple faults using a single coefficient, with the possible overhead being an extra control input.