Showing papers on "Fault detection and isolation published in 1988"

FIAT-fault injection based automated testing environment

Abstract: An automated real-time distributed accelerated fault injection environment (FIAT) is presented as an attempt to provide suitable tools for the validation process. The authors present the concepts and design, as well as the implementation and evaluation of the FIAT environment. As this system has been built, evaluated and is currently in use, an example of fault tolerant systems such as checkpointing and duplicate and match is used to show its usefulness. >

Extraction and simulation of realistic CMOS faults using inductive fault analysis

Abstract: FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults. >

Multiple distributions for biased random test patterns

Abstract: An efficient method has been presented to compute multiple distributions for random patterns, which can be applied successively. Using multiple distributions, all combinational circuits can be made random-testable, and complete fault coverage is provided by a few thousands of random patterns. The differently weighted random test sets can be applied to scan path circuits using an external chip, combining the advantages of a low cost test and of high fault coverage. Several facts about testing by random patterns have been proven. It has been shown that the number of random patterns required for a certain fault coverage can be computed without regarding the pseudorandom property and with the independence assumption for fault detection. >

Travelling wave distance protection-problem areas and solutions

Abstract: The authors examine some problem areas and suggest techniques to improve the proposed distance protection based on travelling waves outlined by P.A. Crossley and P.G. McLaren (1983). A composite correlation output is used to recognize the reflection from the fault and distinguish it from other reflections from points behind the fault. The correlator output magnitude is also used to achieve UHS (ultra high speed) fault detection for close-up faults. Effects of fault inception angle are compensated. Fault-resistance effects and external faults are also examined. >

Detecting bridging faults with stuck-at test sets

Abstract: A method is described that provides high detection of bridging faults without requiring extensive fault simulation. Bridging fault coverage can be increased by doing fault simulation and test generation for bridging faults that are identified as hard to detect. These bridging faults occur between nodes that rarely, if ever, differ, or that seldom change value. In addition, if the nodes in the fault-free circuits toggle often, feedback faults are easier to detect. This is true even if the nodes involved always have equal values. Methods for identifying such nodes have been presented. These methods use results available from fault-free simulations. A simple solution is to randomly reorder the test vectors to increase toggling and therefore increase bridging fault coverage. As a result, computer time for test generation will be only slightly greater than the time required for stuck-at fault generation alone. >

On-line hazard aversion and fault diagnosis in chemical processes: the digraph+fault-tree method

Abstract: A method for online hazard aversion and fault diagnosis in chemical processes is developed. The method uses a directed graph model of process operation and control. Fault trees developed from the directed graphs are combined with real-time data to provide online diagnosis for hazard aversion and fault detection. Both hardwired control and manual control are modeled. A single control loop illustrates the modeling technique and the diagnosis method. The method provides an advance alert to process problems and an identification of the problems' causes, based on the available real-time data and prior rates of equipment malfunctions and process disturbances. >

An arcing fault detection technique using low frequency current components-performance evaluation using recorded field data

Abstract: Several low frequencies of the current waveform in distribution feeders exhibit modified behavior under fault conditions. Two frequencies, 180 Hz and 210 Hz, were selected for study owing to the strong magnitude variations associated with arcing faults at these frequencies. A hierarchical algorithm with adaptive characteristics is presented along with the performance results for its application at these low frequencies. The various parameters that affect the sensitivity of the algorithm are discussed. The results of tests using recorded field data are given, and the effects of using a digital filter front end for the algorithm are also discussed. >

Fault detection effectiveness of weighted random patterns

Abstract: Performance results are given for use of a weighted random pattern test generator, WRP, on ten benchmark designs. Deterministic (DET) and WRP tests created for single stuck faults are compared in their ability to detect shorts and transition faults. The WRP is able to generate a test for all the single stuck faults detected with a state-of-the-art deterministic pattern generator; WRP is highly efficient in CPU time required for full stuck fault test pattern generation; both DET and WRP achieved high net-to-net shorts fault coverage on a sample of ten designs; and WRP had significantly higher ( approximately=11%) transition fault coverage than obtained with DET for the same sample. >

A method of delay fault test generation

Abstract: It has been observed that random testing for delay faults can result in test sets of excessive length and high simulation costs. Consequently, we propose an efficient deterministic method of delay fault test generation. For most common circuits, our proposed technique has a time complexity which is polynomial in the size of the circuit, as opposed to existing deterministic methods which, for nearly all circuits, are exponential. We define a type of transition path, the fully transitional path, FTP, and demonstrate that it has several useful properties. An FTP can be created by applying a vector pair derived from a stuck-at test for a primary input, a technique introduced in [1]. We extend this method by using an alternate representation for switching functions, the binary decision diagram, to generate graphs representing stuck-at tests. The concept of free variables is defined as a tool for deriving several FTPs from one stuck-at test. Preliminary results are presented which indicate that our method provides a higher robust delay fault coverage than psuedorandom patterns at less than one-fifth the cost. Also, since vector pairs cannot be applied to combinational circuits using standard scan design, a simple scannable latch is introduced to facilitate this task.

Fault tolerant computer systems with fault isolation and repair

Abstract: A fault tolerant computer system has a central processing system which includes at least one set of data pathways, and executes a series of data processing instructions including the transfer of messages along the plurality of data pathways. At least one set of transaction data storage devices are coupled to the data pathways for storing a predetermined number of successive messages transferred most recently on the data pathways. Error checking devices are included for detecting the presence of errors in the central processing system. Error storage devices are coupled to the transaction data storage devices and the error checking devices for causing the transaction data storage devices to cease storing additional messages in response to the detection of errors by the error checking device.

Fault detection and diagnosis of automated manufacturing systems

Abstract: The authors develop a controller methodology for fault detection and diagnosis using Petri nets and fault trees in automated manufacturing systems. The controller has two levels. At the first level there are dedicated diagnostic systems for each of the subsystems, such as machine centers, robots, conveyers, etc. At the second level there is an intelligent controller monitoring the part flow and coordinating the local diagnostic systems and controllers. The authors assume that local controller and diagnostic systems exist for subsystem-level fault detection and diagnosis, and they present a Petri-net-based intelligent controller for system-level fault detection and diagnosis. The authors also describe fault-free-based diagnostics. >

MOZART: a concurrent multilevel simulator

Abstract: MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimizes the number of events and evaluations, and list event scheduling, which allows optimized processing of simultaneous (fraternal) events for concurrent machines. Moreover, efficient handling of abnormally large or active fault machines can improve fault-simulator performance by several orders of magnitude. These and related issues are discussed; both analytical and experimental evidence is provided for the effectiveness of the solutions adopted in MOZART. A performance metric is introduced for fault simulation, based on comparison with the serial algorithm, and is more accurate than those used in the past. >

Robust Observer Design with Application to Fault Detection

Abstract: A new scheme for robust estimation of the partial state of linear time-invariant multivariable systems is presented, and it is shown how this may be used for the detection of sensor faults in such systems. We consider an observer to be robust if it generates a faithful estimate of the plant state in the face of modelling uncertainty or plant perturbations. Using the Stable Factorization approach we formulate the problem of optimal robust observer design by minimizing an appropriate norm on the estimation error. A logical candidate is the 2-norm, corresponding to an H? optimization problem, for which solutions are readily available. In the special case of a stable plant, the optimal fault diagnosis scheme reduces to an internal model control architecture.

High resistance ground fault protection

Abstract: A protection device for high resistance ground faults in a power network according to the invention has a fault detection principle which is based on an indirect study of non-harmonic frequency components of the phase currents. When such a fault has occurred, a considerable change of the energy contents of these frequencies arises. This change can be detected by a device according to the invention. If by comparison (4e) between digitized input signals (I') and a harmonic Fourier model (4d) of the same signals, i.e. generation of the residuals of the system, it is found that a difference exists, and if the corre-sponding loss function VN (4f) for a certain time exceeds a lower limit value - all on condition that a zero sequence current (Io) exists - then there is a high resistance ground fault on any of the phases of the network. (Figure 2)

Fault Detection and Design For Testability of CMOS Logic Circuits

Abstract: Advances in integrated circuit technologies have made complementary MOS (CMOS) the preferred MOS technology for digital logic circuits. Cost effective design and fabrication of reliable CMOS VLSI chips require understanding of various CMOS technologies, logic families, failure modes, fault detection methods and design for testability methods. In this paper we will review some of the basic methods and issues related to the design and fault detection of CMOS logic circuits.

Fault detection of combinational circuits based on supply current

Abstract: A fault detection technique is proposed which can detect logical faults in combinational circuits by measuring the supply current instead of the output logic, and the effectiveness is evaluated by experiments of the circuits made of TTL (transistors-transistor logic) ICs. This technique is based on the assumption that the supply current will be changed by faults in the logic circuits. A generation mechanism of current variation is represented by an autoregressive model, and faults are detected by using pattern-recognition methods. >

Testing for multiple faults in domino-CMOS logic circuits

Abstract: The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view. >

Robust fault diagnosis using the model-based approach

Abstract: Focuses on the state (or output) estimation approach to FDI. In particular, the interest is in the use of robust observers or robust state estimators which have the designed capability of discriminating between effects due to unknown inputs, disturbances and actual faults. There is always a difference between actual process parameters and those of the nominal model used in the observers (or Kalman filters). The effect of parameter variations obscures the effect of fault detection in that it acts like noise as a source of probable false alarms. The objective of this work is to provide an introduction to the subject of fault detection and isolation in dynamic systems so that the reader may know where to turn for definitions and for reference material. The authors provide an extensive historical review of the subject. Finally, they provide the basic mechanism of an FDI scheme based on the use of the so-called General Observer Scheme (GOS) for fault detection. Results are given to show the potential of the method when applied to a (simulated) nonlinear aircraft system. >

Multiple fault detection using single fault test sets

Abstract: A simulation study of the 74LS181 4-b ALU (arithmetic logic unit) using 16 complete single stuck-at fault test sets demonstrated significantly higher multiple stuck-at fault coverage than predicted by previous theoretical studies. Analysis of the undetected multiple faults shows the effect of circuit and test set characteristics on fault coverage. A fault masking property, defined as self-masking, is observed for the undetected faults in the simulation study. A heuristic is described for evaluating the multiple fault coverage of single stuck-at fault test sets. A second heuristic generates augmented test sets, providing improved multiple stuck-at fault coverage with a minimal increase in test set development cost. >

Fault detection in combination intrusion detection systems

Abstract: An intrusion detection system employs a microwave subsystem and a passive infra-red subsystem. Both systems must produce an output signal indicative of an intrusion in order for the system to produce an alarm. There is disclosed a supervision circuit which monitors the number of trips of the microwave system as well as the number of trips of the PIR system. If the number of trips which are indicative of false alarms exceeds preset counts then an alarm is produced indicating that there is a failure in the microwave or the PIR system. The system further monitors the microwave system to determine whether the transmit and receiving diodes are functioning properly. The system will also indicate a fault if an intruder or an object is placed within a predetermined protection dome implemented by the system. Hence the system can produce multiple faults indicative of subsystem failures to notify the user of the system that such a failure has occurred.

Memory emulation method and system for testing and troubleshooting microprocessor-based electronic systems

Abstract: A method and system for testing and troubleshooting microprocessor-based electronic systems employs memory emulation techniques as well as other techniques to provide complete functionality tests and fault location. Fine-resolution sync pulses may be generated at preselected time positions during a bus cycle of interest to facilitate full troubleshooting fault isolation. Other features include bus testing using memory emulation techniques, using the chip select line of ROMs to encode test results, and techniques that keep a target microprocessor functioning in a system in which the kernel is dead.

Fault coverage of protocol test methods

Abstract: The authors present an estimation of fault coverage of four protocol test sequences generation techniques (T-, U-, D-, and W-methods) using Monte Carlo simulation on a simple protocol machine. The ability of a test sequence to decide whether a protocol implementation conforms to its specification heavily relies upon the range of faults that it can capture. This study shows that a test sequence produced by T-method has a poor fault detection capability whereas test sequences produced by U-, D- and W-methods have fault coverage comparable to each other and superior to that for T-method on several classes of randomly generated machines used. >

An implementation and analysis of a concurrent built-in self-test technique

Abstract: The authors propose a built-in concurrent self-test (BICST) technique for testing combinational logic circuits concurrently with their normal operation. They also introduce a concept of sharing the test hardware between identical circuits to reduce the overall area overhead. They implemented this technique in the design of an ALU (arithmetic logic unit) with online test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area, and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU. The authors define some measures for evaluating the performance of the BICST technique and discuss methods for their computation and include both simulation and analytical results. In addition to detecting permanent faults, the BICST technique can also be used for detecting intermittent and transient faults. The authors propose some methods for detecting intermittent faults and for computing the transient fault coverage. >

A probabilistic method for fault diagnosis of multiprocessor systems

Abstract: The authors present a system-level fault-diagnosis algorithm for identifying faulty and fault-free units in a homogeneous system of computing elements. The algorithm is based on a comparison approach where tasks are performed by the units and their outputs are compared among themselves. Unlike other approaches, the authors' algorithm requires no global syndrome analysis and therefore can be performed in real time as a background task during system operation. The time required to perform the diagnosis is constant regardless of the number of units in the system. Like previous global syndrome-based approaches, the accuracy of the algorithm is remarkably high, since it uses information about individual comparison results which is lost when these results are summarized in a global syndrome. >

Dual zone, fault tolerant computer system with error checking in I/O writes

Abstract: A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism. Fault detection devices are coupled to the first and second data output terminals for comparing the data output from the first processing system with the data output from the second processing system. The fault detection devices identify the presence of an error when the data output from the first processing system at the first output terminal is different from the data output from the second processing system at the second output terminal.

Fast generation shedding equipment based on the observation of swings of generators

Abstract: A novel method and recently developed stabilizing equipment to prevent the loss of synchronism of generators in pumped-storage plants due to spreading are presented. The method includes functions to estimate the swing of each generator by using online generator output sampled 600 times per second after an occurrence of a disturbance (such as a fault, faulty equipment, etc). Generator swing 200-300 milliseconds ahead and loss of synchronism between generators in pumped-storage plants and those in thermal and nuclear plants can be predicted 200-300 ms ahead, and the number of generators that must be shed to maintain stability can be decided. >

Electrical fault protection for a large photovoltaic power plant inverter

Abstract: The authors analyze the original protection design and describe changes made to improve fault protection after electrical faults caused fires in the DC wiring of a photovoltaic (PV) power plant. The zone-of-protection was extended, and fault detection and response were improved. The results suggest a need for better coordination between DC and AC fault protection philosophies that are commonly applied independently by designers. Design lessons for PV array fault protection are described to assist electrical designers in eliminating fault vulnerabilities from future PV systems. These take into account the unique electrical characteristics of PV generators, including the dispersed-rather than point-source and the current- rather than voltage-source nature of the PV array. >

Multiple stuck-open fault detection in CMOS logic circuits

Abstract: It is shown that a test set based on two-pattern tests, which are designed to detect single stuck-open faults, can be found that detects all multiple stuck-open faults inside any CMOS gate in the circuit. The concept is extended to three-pattern tests, which are obtained for every single stuck-open fault at the checkpoints. If a certain condition is satisfied, then it can be shown that the resulting test set can detect any multiple stuck-open fault in the circuit. Even when this condition is not fully met, a very large percentage of the multiple stuck-open faults can still be guaranteed to be detected. For the special case of fan-out-free CMOS circuits, it is shown that a single stuck-open fault test set based on two-pattern tests can always be found that has 100% multiple stuck-open fault coverage. This test can also be guaranteed to be robust in the presence of arbitrary delays. >