Showing papers on "Fault indicator published in 1976"

System for disabling the reset circuit of fault indicating means

Abstract: The reset circuit of a fault indicator is disabled to prevent automatic restoration of the movable target from fault indicating position where it can be observed and manually rest. A manually operable switch is connected across the reset ciruit and its contacts are closed by permanent magnet means or by manually operable switch means.

Fault indicator and means for resetting the same

Abstract: A fault indicator for alternating current distribution systems includes a pair of spaced pole pieces for receiving therebetween at one end the conductor and at the other end a pivoted permanent magnet carrying a target that is biased to a fault indicating position by a stationary permanent magnet. The pole pieces are demagnetized on flow of fault current in the conductor. They are remagnetized by a winding which is energized by discharge of a capacitor that is charged through a rectifier from an oscillator circuit. The winding is carried by a receptacle into which the other ends of the pole pieces are inserted and a circuit is completed thereby to charge the capacitor. The receptacle is carried at one end of a tubular housing the other end of which has an eye to receive a claw of a live line tool for applying the fault indicator to and removing it from the conductor.

A Logic System for Fault Test Generation

Abstract: This paper describes a logic system specifically designed for fault test generation. The system allows the user to impose a set of initial constraints on the elements of a logic network by indicating those values which an element may (or may not) assume for the test under consideration. He can be as vague or as specific as he wants in imposing these constraints. A set of logic tables is then used to automatically propagate the effects of these constraints throughout the network. As a result of this logic propagtion, the necessary values of the elements in the network become much more precisely (if not completely) defined. The tables also indicate whether or not the generated test (which may include a number of unspecified values) is sufficient to detect the given fault. If several different tests will suffice, the choices remaining are clearly indicated. In the case of a redundant lead (untestable fault), propagation through the tables automatically results in a logical inconsistency.

Fault detection and system for electrostatographic machines

Abstract: A xerographic type copying or reproduction machine incorporating a programmable controller to operate the various machine components in an integrated manner to produce copies is disclosed. The controller carries a master program bearing machine operating parameters from which an operating program for the specific copy run desired is formed and used to operate the machine components to produce the copies programmed. A fault flag array is routinely scanned, each flag comprising the array being associated with an operating component or area of such machine such that on a fault or malfunction thereof, the fault flag corresponding thereto is set. On detection of a fault flag, a machine fault is declared. Display means are provided to visually identify the fault location. A permanent record of certain faults and machine operations are stored in memory for future use.

Fault indicator responsive to flow of fault current in a conductor when power flow is in one direction only

Abstract: The occurrence of fault current flow in an alternating current carrying conductor is indicated if the power flow in the conductor is in one or a preferred direction and is not indicated if the power flow in the conductor is in the opposite direction.

Fault indicator for motor vehicle battery charging systems

Abstract: A fault indicator for a motor vehicle battery charging system of the type in which a diode-rectified alternating current generator supplies charging current to the vehicle battery and supplies other loads on the vehicle. The fault indicator is capable of detecting certain faults in the diode-rectified alternator and is capable of detecting certain faults in the generator voltage regulating system. The fault indicator system utilizes current difference operational amplifiers, one of which is connected to detect sharp negative voltage transitions caused by certain faults in the system. The fault indicator also has Zener diodes connected to provide an indication of faults that cause abnormally low or high voltage outputs of the diode-rectified alternator such as an open or shorted voltage regulator. The signal indicator utilized is a light emitting diode and the fault indicator circuit is arranged so as to cause continuous illumination of the light emitting diode under certain fault conditions and a blinking of the light emitting diode during other fault conditions.

Tool for manually tripping a fault indicator for high voltage electric power circuits and resetting same

Abstract: This invention relates, generally, to fault indicators and it has particular relation to tools for testing fault indicators of the kind and character disclosed in my U.S. Pat. No. 3,906,477, issued Sept. 16, 1975.

Identification of Multiple Stuck-Type Faults in Combinational Networks

Abstract: This paper deals with the problem of identifying multiple stuck-type hardware failures in combinational switching networks. Our work is an extension of that of Poage, and Bossen and Hong, and we employ the cause-effect equation for representing faulty circuit behavior. We introduce the concept of solving simultaneous equations over check point variables. These check point solutions are studied in detail. From the solutions one can calculate the function realized by a faulty circuit. We outline an on-line testing procedure for constructing a test set for identifying a specific fault in a circuit to within an equivalence class. This procedure eliminates the need for precalculating a fault dictionary, which, in many instances, can be quite advantageous. We also outline how to apply these techniques to the following problems: 1) identifying redundancy; 2) determining the set of faults not detected by an arbitrary test set; and 3) constructing a complete fault dictionary.

People-protecting ground fault circuit interrupter

Abstract: A ground fault circuit interrupter comprises separable contacts for interrupting current flow through a power circuit being protected, trip means operable upon energization to effect separation of the contacts, means for detecting ground fault current, means for monitoring voltage upon the power circuit, and means responsive to the ground fault current detecting means and the voltage monitoring means for energizing the trip means when ground fault current reaches a trip current level. The trip current level varies as a function of the power circuit voltage.

Fault indicator testing apparatus

Abstract: Apparatus provides for testing a fault indicator of the type which has a surge-current detection portion and a settable fault indicating portion and which is widely used in electric power distribution systems. Such a fault indicator must meet certain performance specifications including a maximum allowable reaction-time specification relating to the time required for the detection portion first to detect a surge current flowing in a conductor as a result of a down-line fault and then to set the fault indicating portion accordingly. The testing apparatus of this invention provides for effectively simulating field conditions, and to this end includes current-drive circuitry for supplying a test surge current to the fault indicator under test. Substantially simultaneously with the start of the test surge current, a timing-initiation signal is produced to enable interval-timing circuitry in the testing apparatus. To designate the end of the interval being timed, there is produced a timing-completion signal. Preferably, an optical sensing arrangement responsive to the fault indicator provides the timing-completion signal. The testing apparatus includes a display responsive to the interval-timing circuitry to show test result data as to the reaction time of the fault indicator under test.

The application of cepstrum technique in power cable fault detection

Abstract: A technique for detecting power cable fault is described. The cable faults are usually characterized by degradation of the dielectric, either by water inclusion or physical cracking and associated voids. Voltage reflected at the fault is modeled as distorted echo. In this technique, a voltage step test signal propagates down the line and reflects energy when a change in impedance occurs. Digitized samples are taken along the return waveform. The power cepstrum of the data is then computed; a simple echo of delay τ produces a ripple in the cepstrum domain of quefrency τ yielding information about the fault location.

Arrangement for fault diagnosis in the communication controller of a program controlled data switching system

Abstract: Apparatus is described for monitoring and diagnosing faults in the communication controller of a line termination unit in a program controlled data switching system. Individual devices detect faults and emit fault signals using safeguarding programs for the fault diagnosis. The communication controllers each contain a fault collection device which receives the individual fault signals and forms a fault word therefrom which describes the fault. Further, fault reaction signals are formed. A diagnosis routine device evaluates a diagnosis command read out from the diagnosis zone of a central storage unit. The diagnosis routine device contains a first decoding circuit for decoding the operations portion of the diagnosis command and for forming control signals therefrom. The control signals cause data channels to be switched through between the word output register and the word input register, as well as between a fault word register containing the fault word in the fault collection device and an intermediate buffer store. A second decoding circuit in the diagnosis routine device is activated by an additional control signal for producing a second series of control signals by evaluating a command of the diagnosis command. The control circuits and registers of the communication controller are connectable to the word input register under the control of the second control signals for the transfer of the diagnosis command.

A new mathematical analysis of series and shunt faults on three phase power networks

Abstract: A mathematical analysis of sequential fault transients due to series and shunt faults is important in the study of circuit breaker pole openings and reclosings with arc resistances. The line loading itself becomes unbalanced momentarily due to load switching. Each double fault is developed in sequence, therefore the initial currents in the second and third fault must be treated properly under transient conditions. New sequence component variables λμ0 and ρσ0 are used with αβ0 components. This study is useful for small power systems as well for large power systems. A digital simulation of various series and shunt faults is presented in a generalized manner using αβ0, λμ0 and ρσ0 components.

Partitioning logic circuits to maximize fault resolution

Abstract: Two techniques are discussed for partitioning logic circuits to maximize the resolution of stuck-line faults. One technique exploits the inherent fault resolution of the circuit by attempting to force equivalent faults into the same module. The other involves inserting control points to separate members of equivalent fault classes, a technique called fault class splitting. Some new methods for identifying equivalent faults are also presented.

Dental operational condition indicator - is for supply circuit unit with LED's indicating faults in printed circuit panels

Abstract: Operational condition control indicator is for a dental supply circuit unit with individual electrical circuit parts on interchangeable circuit panels in a printed circuit technique whereby each individual circuit part has a fault indicator in the shape of a light diode (4) coupled to a reference element and responding to a faulty function i.e. too high or too low potential or too high or too low current and thus actuating the fault indicator (4). Pref. a fault indicator (4) is provided for each consuming device (1) in the unit i.e. drills, handpieces, breaker fillers or basin flushing equipment etc. Thus system aids rapid location of fault without necessarily calling upon highly skilled technical assistance.

An Integrated Circuit Fault Model for Digital Systems.

Abstract: : A model for the faulty behavior of digital networks realized using integrated circuit devices is proposed This model, the pin fault assumption, is based on a study of the most frequently encountered failure mechanisms for such networks, and the observation that previous fault assumptions model a large number of faults which occur with low frequency The basis for the pin fault model, and an investigation of multiple fault detection using this model are presented Fault detection for combinational modules is investigated, and it is shown that multiple pin fault detection test sets for such modules may be quite easily generated The computation required to generate such test sets is independent of the circuit realization internal to the model, and each test generated requires about the same amount of computation The computational complexity of test generation is greatly reduced compared to that for previously studied fault models Pin fault detection experiments for sequential machines are studied, and methods for designing such experiments are developed These design methods are compared to those under other fault assumptions, and a substantial reduction is observed in the length of such sequences and the computation required to produce them (Author)

Fault Detection Problems and their Impact on the Design of Digital Circuits

Abstract: This communication presents the principal methods for detecting faults in logical structures. As a consequence of their limitations (size of the structures) methods for modifying the circuits in order to obtain easily testable and/or self-checking systems are given.