Showing papers on "Fault indicator published in 1980"

Measures of the Effectiveness of Fault Signature Analysis

Abstract: A linear feedback shift register can be used to compress a serial stream of test result data. The compressed erroneous bit stream caused by a fault is said to form the "signature" of the fault. Since the bit stream is compressed, however, it is possible for an erroneous bit stream and the correct one to result in the same signature.

Automatic fault diagnostic apparatus for a heat pump air conditioning system

Abstract: Microprocessor controlled apparatus is provided for automatically diagnosing faults in a heat pump system. Temperature sensors located at strategic points in the system are read periodically in accordance with a preprogrammed diagnostic routine. Temperature measurements preferably representing comparison of two temperature readings that produce temperature differentials outside pre-established tolerance limits are stored with a fault identification representative of the corresponding fault measurement. A service technician can read the fault data from storage by activation of control means for that purpose whereby the nature of the causative fault or faults can readily be determined.

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis

Abstract: In this paper we present a new approach to multiple fault diagnosis in combinational circuits based on an effect-cause analysis. The main vehicle of our approach is the deduction of internal line values in a circuit under test N*. The knowledge of these values allows us to identify fault situations in N* (causes) which are compatible with the applied test and the obtained response (the effect). A fault situation specifies faulty as well as fault-free lines. Other applications include identifying the existence of nonstuck faults in N* and determination of faults not detected by a given test, including redundant faults. The latter application allows for the generation of tests for multiple faults without performing fault enumeration.

Fault Diagnosis Based on Effect-Cause Analysis: An Introduction

Abstract: This paper presents the basic concepts of a new fault diagnosis technique which has the following features: 1) is applicable to both single and multiple faults, 2) does not require fault enumeration, 3) can identify faults which prevent initialization, 4) can indicate the presence of nonstuck faults in the D.U.T., 5) can identify fault-free lines in the D.U.T. Our technique, referred to as effect-cause analysis, does not require a fault dictionary and it is not based on comparing the obtained response of the D.U.T. with the expected response, which is not assumed to be known. Effect-cause analysis directly processes the actual response of the D.U.T. to the applied test (the effect) to determine the possible fault situations (the causes) which can generate that response.

Distributed Fault-Tolerant Computer Systems

Abstract: Modular systems employing building-block VLSI circuits may provide fault tolerance to a variety of applications.

Ground fault circuit breaker with ground fault trip indicator

Abstract: A ground fault circuit breaker including ground fault interruption means and overload interruption means that are independently responsive to open a common set of breaker contacts upon respective ground fault and overload conditions with a trip indicator visible external to the breaker that operates on actuation of the ground fault interruption means but not upon operation of the overload interruption means with means for electrically actuating the trip indicator upon occurrence of a ground fault condition that actuates the ground fault interruption means.

Self-diagnosing, self-correcting communications network

Abstract: A ring-configured network of multiple inter-communicating data stations in which each data station includes a fault sensing circuit, a test-pulse generating circuit and a switching circuit as well as a transmitter circuit and a receiver circuit, and the test pulse generating circuit responds to a sensed fault to transmit, sequentially, in opposite directions along the ring, test signals which, in combination with the fault sensing circuit, indicate the direction of any fault and terminate the line in the direction of the fault at the characteristic impedance of the line. Thus, normal communications can continue between the stations despite the fault.

Ground fault indicator

Abstract: A ground fault indicator for a multi-phase power distribution system includes a split-core magnetic pole assembly having a gap within which is developed a magnetic flux representative of the vector sum of the currents in the individual phase conductors of the system. A magnetic reed switch positioned within the gap responds to the summation current in the gap to trip an indicating circuit in a remotely mounted indicating module in the event of a ground fault.

Fault indicator with flux concentrating means

Abstract: A fault indicator for indicating the occurrence of a fault current in an electrical conductor includes an externally viewable target which is positioned to a fault-indicating position by a trip circuit within the indicator upon occurrence of a fault current. The trip circuit is responsive to a magnetic field within a predetermined sensing plane generally parallel to the conductor. To increase the sensitivity of the indicator to the magnetic field of the conductor, the fault indicator includes flux concentrating pole pieces which form a low reluctance magnetic circuit between the circumference of the conductor and the sensing plane.

Bus fault detector

Abstract: The present invention comprises computer system equipment useful for detection of faults in data transmission within a computer system. Fault detection is accomplished by monitoring the current flow through a digital signal source means, which is characterized in that it only draws significant current during a non-transition period when a fault condition occurs.

Fault detecting sensor and method of detecting faults therewith

Abstract: This invention relates to sensors for detecting a fault condition, e.g. excessive temperature or leakage of fluid, in a large apparatus, and to methods of using such devices. The novel sensors comprise a conductor, an element composed of a conductive polymer whose resistivity increases sharply when a fault condition occurs, and a dielectric element which separates the conductor and conductive polymer element so that they form an electrical capacitor. The sensor is in the form of a sheet or cable whose capacitance is periodically measured. When a fault condition occurs, the conductive polymer element increases sharply in resistance in the region of the fault and reduces the capacitance of the sensor, thus signalling the occurrence (and preferably also the location) of the fault. Figure 1 shows a typical sensor in the form of a cable comprising a central conductor 10, a dielectric layer 12, a PTC layer 14 and on outer protective layer 16. The invention is particularly useful for detecting localised overheating, e.g. in dryers for agricultural products, or leakage of a fluid, e.g. from a conduit.

Fault identification in electric power transmission systems

Abstract: A method of identifying faults in a polyphase alternating current electric power transmission system wherein determination of the type of fault occurring is effected by monitoring, using analogue techniques, the instantaneous values of quantities derived from superimposed currents and/or voltages arising in the system on occurrence of a fault. Apparatus for carrying out the method is also disclosed.

Reliability Implications in the Design of Fault Current Limiters

Abstract: This paper is principally concerned with the implications of FCL reliability upon the design and application of fault current limiters. The paper examines the following important questions: I) Can devices which are designed to meet present functional specificationis for fault current limiters be made compatible witlh the implicit need for reliability and economy? 2) Sinice no device will ever be fully reliable, what are the consequenices of FCL failure, anld what constitutes reasonable backup protectioni? 3) Cain the nieeds whlichi have spawned the quest for the FCL be met better in a manner more consistent with the essential needs for economy and reliability by modifying the functional specifications? t 4) For puirposes of backup protection, would a limiter which responds only after the first current loop has been allowed to pass be of any worth? 5) Are there any significant improvements or benefits in the tolerance of apparatus to momentary currents if severe fault currents are limited to a single current loop?

Deciding system for cause of plant fault

Abstract: PURPOSE:To treat a fault effectively while relieving an operator from the load of investigating the cause, by obtaining information effective to the investigation on the cause of the fault from the change of data before the fault is detected in the occurrence of the fault. CONSTITUTION:Data of each plant up to the detection of a fault by a fault detector 3 is stored previously as a fault cause tree 10, and a data change table 9 containing the tree 10 and the change of data before the fault is detected, and a secular value table 8 recording data in the detection of the fault are used to analyze the cause of the fault. Then, a fault cause deciding device 6 analyzes the cause of the fault from the tree 10 and the result of it is displayed 7. Here, the tree is displayed to display the change and path of the plant data understandably. Since the time when the data changed is also stored in the table 9, it is displayed simultaneously. Consequently, a plant fault is treated rapidly and adequately.

Method and apparatus for fault identification in electric power transmission systems

Abstract: A method of identifying faults in a polyphase alternating current electric power transmission system wherein determination of the type of fault occurring is effected by monitoring the amplitudes and relative phases of fault current quantities derived from the phase currents of the system. The current quantities are preferably phase fault currents and quantities derived by addition and subtraction of phase fault currents. Apparatus for carrying out the method is also disclosed.

An Accurate Functional Level Concurrent Fault Simulator

Abstract: This paper describes the basic data structures and algorithms for a functional level fault simulator The technique used is that of concurrent fault simulation The algorithms and data structure support multi-signal value, gate and functional level device models These algorithms and data structures also support the capability to simulate user defined faults and faults that cause timing violations In the experimental version of the system, developed at the University of Texas, only classical stuck-at faults and faults that lead to timing discrepancies between the good and the faulty circuit were implemented Minor additions to the data structures will allow the simulator to process non-classical faults like: (1) memory stuck-at, (2) user defined functional faults, (3) technology dependent shorted signal faults, etc The accuracy achieved simulating a fault is consistent with the accuracy of the non-fault model

Power cable fault finding apparatus and method

Abstract: An inductance coil is clamped onto the cable which is to be monitored. For normal line currents, the coil produces a signal voltage which charges a reset capacitor which in turn periodically discharges to an indicator to show a no fault condition. When the line current goes above a predetermined fault level and remains at that level for a corresponding fault time period, the coil develops a signal voltage sufficiently high to charge a "set" capacitor that discharges to the indicator to show a fault condition. The indicator continues to show the fault condition until normal current has returned to cause the "reset" circuit to operate to indicate no fault. To insure that the set capacitor discharges in a manner to indicate reliably the fault condition, there is provided a voltage responsive variable impedence in the circuitry to charge the set capacitor. This variable impedence matches the fuse characteristic in the main power line.

Fault detection in integrated circuit chips and in circuit cards and systems including such chips

Abstract: VLSI chips contain a very high density of logic elements and have only a limited number of pin connections making complete testing by conventional means impracticable. The invention provides a self-verifying chip. The chip includes a data processing chain (10) and a plurality of fault detecting circuits (13,14,15) coupled to the data processing chain. A plurality of internal stimulus generators (18,19,20) generate test signal patterns in response to a supervisory control (21) which are applied to intermediate points of the data processing chain. Outputs from the fault detecting circuits (13,14,15) are applied to an error status generator (16) which provides error signals indicating fault conditions at various points of the data processing chain. Fault detecting circuits (18A.21A) may also monitor the internal stimulus generators and the supervisory control means. The devices of the data processing chain may normally operate in a parallel-load mode, but may be loaded with the test signal patterns in serial mode. The chip may include duplicate functional or complementary logic for the data processing chain, and the fault detecting circuits may be arranged to check the operation of the two logic chains against each other. A number of chips according to the invention may be mounted on a card, with a card fault detector receiving the outputs of the error status generators of the chips and providing an output indicating the faults detected in the chips and in the card wiring, and, in turn, in a complete system the outputs of the card fault detectors may be applied to a system fault generator monitoring the occurrence of faults in the whole system.

An Optimized ATPG

Abstract: This paper describes a hierarchical approach to the detection of the critical faults of a digital board, i.e., those most likely to occur. The failure probabilities of the nodes of a board are estimated and used as weights in selecting the nodes for fault detection. The study has indicated both a saving in pattern generation and a higher fault detection per pattern. This approach introduces a new definition of fault coverage. The approach is also applicable to analog circuits. In addition, it allows for continual incorporation of field data, thus improving the estimation of the failure probabilities.

Address-less fault location for digital transmission systems - uses transmission of identical fault locating signals with same sign by testing end stage, affecting loop formation on output lines

Abstract: The addressless fault localizing process for digital transmission operates with intermediate stations, which contain regenerators in the separate transmission lines and loop forming devices from the one to the opposite direction of transmission. A testing terminal station transmits fault local signals along the outgoing transmission line. The terminal station transmits only like fault locating signals with the same characteristic sign. These signals effect progressively on the outgoing transmission line both the loop formation and are used in the terminal station to detect faults or to locate the fault. At the beginning of the fault location, during the first fault locating signal transmission, a counting station for each regenerator of the outgoing transmission direction is trigerred. This system requires little instrumentation and is simple.

Fault indicator for control circuit of laser - has display circuit and display triggering circuit between power supply and CW controller

Abstract: The fault indicator has a display (17) and display triggering circuit (24) connected between the CW controller (8) and the power supply. The display circuit (17) contains a common-emitter transistor (18) with an indicator lamp (19) in its collector circuit and connected by its base via a resistor (21) to the output of the controller. The display triggering circuit contains a transistor (26) whose collector is connected to the control voltage, whose base is connected to the power supply of the laser and whose emitter contains a variable reference voltage source (27).

Method and apparatus for identifying faults in electric power transmission systems

Abstract: A method of identifying faults in a polyphase alternating current electric power transmission system wherein determination of the type of fault occurring is effected by monitoring, using analogue techniques, the instantaneous values of quantities derived from superimposed currents and/orvoltages arising in the system on occurrence of a fault. Apparatus for carrying outthe method is also disclosed.

Fault detection in combinational circuits using a compressed fault table

Abstract: A method is developed for obtaining a highly compressed fault table for two-level combinational circuits. A set of operations is defined through which the minimal test set for detecting stuck-at faults is obtained from the compressed fault table. The method is equally suitable for sum of products form or product of sums form realization of logic functions and generates the test set directly from the algebraic expression of the logic function.