Showing papers on "Fault indicator published in 1981"

Fault-Diagnosis for a Class of Multistage Interconnection Networks

Abstract: To study the fault-diagnosis method for a class of multistage interconnection networks a general fault model is first constructed. Specific steps for diagnosing single faults and detecting multiple faults in interconnection networks such as the indirect binary n-cube network and the flip network are then developed. The following results are derived in this study: 1) independent of the network size, only four tests are required for detecting a single fault; 2) the number of tests required for locating a single fault and determining the fault type ranges from 4 to max(12, 6 + 2 ⌈log2(log2N)⌉) except for four types of single faults in the switching elements which cannot be pinpointed at the switching element level where N is the number of inputs/outputs; 3) only four tests are required for locating a single fault if the switching element is designed in such a way that any physical defection of the switching element causes both outputs of the related switching element to be faulty; and 4) multiple faults can be detected by 2(1 + log2N) tests.

A Fundamental Concept for High Speed Relaying

Abstract: This paper describes a fundamental approach for detecting the direction to a power system fault within the first milliseconds following the fault inception. The method is based on a combined evaluation of the voltage and current deviations generated by the fault occurrence. Design considerations and test results based on numerical simulations and on a transient network analyser are presented. The method solves several problems occurring in conventional relaying and is suitable for use in ultra high speed protection systems which employ a fast telecommunication channel between the ends of the protected network

Automatic Test Generation for Stuck-Open Faults in CMOS VLSI

Abstract: Because of its relative low power dissipation, intermediate speed, and high density, CMOS (Complementary Metal Oxide Semiconductor) will emerge as one of the leading VLSI technologies. Therefore, testing CMOS VLSI circuits is very important. The conventional stuck-at fault assumptions are not sufficient for modeling some faults that are peculiar to CMOS circuitry, specifically the stuck-open faults. These faults are sequential in nature. This means that when a fault occurs in a combinational circuits, the circuit behaves as a sequential circuit. Therefore, special test pattern generation techniques are necessary to test this type of faults. In this paper, we present an algorithm which uses the conventional stuck-at list to detect some stuck-open faults. Some modifications of the conventional testing procedure are necessary. Such modifications and their associated programming effort are expected to be straight forward. For the stuck-open faults that cannot be detected by the conventional stuck-at test list, a second algorithm is described that generates the tests for such faults. The algorithm generates the test if such a test exists. If not, the fault is declared as undetectable. First, we will discuss the stuck-open fault and its peculiarity to CMOS circuitry. Second, we will describe the step-by-step algorithms used to generate a complete test list for this type of fault. Finally, a small example circuit will be used to illustrate the new test generation technique and some conclusive remarks will be given.

Cable mounted magnetic core assembly

Abstract: A fault indicator for indicating the occurrence of a fault current in an electrical conductor includes a core assembly which attaches a circuit module to a monitored conductor and provides a concentrated magnetic flux indicative of the current level in the conductor. A magnetic reed switch in the circuit module responds to the magnetic flux in the core assembly to condition an indicator in a remote indicator module to a fault-indicating state in the event of a fault. To facilitate installation and removal of the circuit module from the conductor, the core assembly is formed by a plurality of laminations secured together and arranged in a generally rectangular configuration with their ends juxtaposed along one side thereof and joined with magnetically conductive interlocking coupling members. A spring spanning the remaining opposed sides of the core biases the coupling members into engagement and allows the structure to be fitted over conductors of various sizes, while maintaining a close operative association between the conductor and the magnetic reed switch in the circuit module.

Fault indicator with combined trip and reset winding

Abstract: A fault indicator for indicating the occurrence of a fault current in a power distribution system includes a test-point-mounted circuit module and a remotely-mounted indicator module. The indicator module incorporates a bidirectional magnetic winding and a magnetic indicating element having a magnetic state conditioned by energization of the winding. Upon the occurrence of a fault in the power system trip circuitry within the circuit module energizes the winding with current in one direction to condition the indicator element to a fault-indicating magnetic state. Upon restoration of current in the system, reset circuitry within the circuit module energizes the winding with current in the opposite direction to condition the indicator to a reset-indicating magnetic state. The use of currents of opposite direction in a single magnetic winding provides greater flux density at the indicating element, and enables the indicator module to be connected to the circuit module by means of a two conductor cable. Alternate embodiments of the invention, utilizing visual-type indicator modules and current-reset modules, are also shown.

Protective relaying methods and apparatus

Abstract: The invention provides methods and apparatus for detecting a single-phase-to-ground fault on a three-phase electrical power system, and for identifying a faulted phase. A single-phase-to-ground fault is correctly distinguished from other faults, including phase-to-phase-to-ground faults, even with transmission lines which utilize series capacitors, by taking into consideration the phase-to-phase voltage which is in quadrature with the voltage to ground of the monitored phase.

Differential fault current protection of a multiprocessor controlled electric power generating system

Abstract: The invention relates to a fault current detection, isolation and clearing system for use in an integrated power generating and distribution arrangement having multiple generators electrically connected to loads and to a distribution bus through circuit breakers. The system includes a power control logic unit and circuit breaker condition detection units which have their outputs electrically coupled to the power control logic unit. Fault current detection circuits are coupled to the electrical connections of the generating and distribution arrangement and have outputs electrically coupled to the power control logic unit. The power control logic unit has an output which is controllingly electrically connected to the circuit breakers to control the circuit breakers and clear faults from the generating and distribution arrangement as a function of circuit breaker conditions and fault currents detected.

A fault isolator for electric utility distribution systems

Abstract: A device (16) for locating faults on the lines (18) of electrical power distribution systems (10), including generally a variable impedance means (26) adapted for connection in series with an electrical power line (18), and means for switching (36) such variable impedance means (26) between a first low impedance value when an initial current I1 of predetermined level flows on the power line (18) for a predetermined period of time to enable detection of a fault condition, and a second high impedance value which limits the flow of current to a low level I2. A meter (46) or other indicating device provides a reading of the current I1 to determine if a fault condition exists. In this fashion, the fault locator device (16) limits both the magnitude and the time duration of the current when testing for a fault, so as not to adversely affect any system components.

Ground fault and fire detector system

Abstract: A ground fault and fire detector system for an A.C. electrical power distribution apparatus including a multi-pole circuit interrupter to disconnect a poly-phase electrical power supply from a load. A single-pole circuit device is operatively connected to the circuit interrupter for controlling its operation. Ground fault sensing circuitry is operatively positioned with respect to at least one wire for initiating a fault current. The single-pole circuit device is responsive to the fault current for activating the circuit interrupter to disconnect the power supply from the load.

Ground fault circuit breaker with mechanical indicator for ground fault trips

Abstract: A ground fault circuit breaker including ground fault interruption means and overload interruption means that are independently responsive to open a common set of breaker contacts upon respective ground fault and overload conditions is provided with a trip indicator visible external to the breaker that operates on actuation of the ground fault interruption means but not upon operation of the overload interruption means, the trip indicator being a mechanical device that is actuated upon the movement of the solenoid plunger that operates upon occurrence of a ground fault condition

Circuit for supervising an electronic electricity meter

Abstract: In an electronic energy consumption meter using a mark-space amplitude multiplier, including a current-frequency transducer, a first supervisory circuit is coupled to, and supervises the mark-space modulator multiplier, a second supervisory circuit is coupled to, and supervises the current-frequency transducer, and a fault indicator is coupled to the output of each of the supervisory circuits for indicating a fault in the meter.

Methodology for measurement of fault latency in a digital avionic miniprocessor

Abstract: Using a gate level emulation of a typical avionics miniprocessor, fault injection experiments were performed to (1) determine the time to detect a fault by comparison monitoring, (2) forecast a program's ability to detect faults and (3) validate the fault detection coverage of a typical self test program. To estimate time to detect, six programs ranging in complexity from 6 to 147 instructions, were emulated. Each program was executed repetitively in the presence of a single stuck at fault at a gate node or device pin. Detection was assumed to occur whenever the computed outputs differed from the corresponding outputs of the same program executed in a nonfaulted processor. Histograms of faults detected versus number of repetitions to detection were tabulated. Using a simple model of fault detection, which was based in an analog with the selection of balls in an urn, distributions of time to detect were computed and compared with those obtained empirically. A self test program of 2,000 executable instructions was designed expressly for the study. The only requirement imposed on the design was that it should achieve 95% coverage. The program was executed in the presence of a single stuck-at fault at a gate node on device pin. The proportion of detected faults are tabulated. In all experiments faults were selected at random over gate nodes or device pins.

Fault indicating circuit for a current consuming load connected to an electronic switching device

Abstract: The invention relates to a circuit for indicating faults in a current consuming load connected to an electronic switching device by means of an indicator device wherein the input of the electronic switching device receives a signal via a control line to cause the load to be switched on. The problem of reducing the number of lines leading to a central operating location is solved in that the input resistance of the electronic switching device is made to be variable by means of an impedance which is controlled by an error signal and the indicator device is actuated in dependence on the current flowing in the control line and emits a fault indication if the current in the control line deviates from the value which it has when there is no fault.

Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits

Abstract: Practical solutions have not been obtained from the previous papers addressing the problem of testing intermittent faults in sequential circuits. Existing methods are only suitable for small sequential circuits. This correspondence presents a new technique to design test-experiments for intermittent faults which can conveniently be used for relatively more complex synchronous sequential circuits.

Single shunt fault diagnosis in a resistive ladder

Abstract: The problem of locating a single shunt fault in a uniform resistive ladder network is considered. A simple method, based on resistance measurements is proposed for the case where the total number of nodes is small and all of them are accessible. Two strategies are discussed for reducing the number of measurements when the number of nodes is large but all nodes are still accessible. When internal nodes are not accessible, it is shown that in theory, it is possible to locate the fault from two resistance measurements at the ports. However, when the number of nodes is large, and the fault is well inside the ladder, such a method is susceptible to large errors. Experimental results are given for some representative ladders.

Synchronism fault detection system

Abstract: PURPOSE:To bracket a fault point instantaneously by monitoring a synchronism fault through an in-use device and a stand-by device which is made hot simultaneously, and collating their results with each other. CONSTITUTION:Information from an incoming-side circuit Wi is passed through the multiplexing part 2, channel 3, and demultiplexing part 4 of an in-use system, and sent out to an outgoing-side circuit Wo through a switching circuit 5. At this time, the multiplexing part 2', channel 3', and demultiplexing part 4' of a stand-by system are made hot. Multiprocessing synchronizing devices 10 and 10' are connected to the channels 3 and 3' to detect a synchronism fault; pieces of fault information are collated with each other by a collating circuit 11, and the outputs of the demultiplexing parts 4 and 4' are collated with each other by a collating circuit 12. When an exchange is normal and a fault occurs on the transmission line, outputs of the circuits 11 and 12 are both 0, and the devices 10 and 10' judge in which circuit the fault occurs from a time slot number. When the transmission line is normal and a fault occurs to either of the channels 3 and 3', the outputs of the circuits 11 and 12 are 1. When a fault occurs between either of channels 3 and 3' and the output side, the output of the circuit 11 is 0 and the output of the circuit 12 is 1.

Fault display device

Abstract: PURPOSE:To display the order of faults and its contents based on the contents of the states of a fault detecting signal, etc. which are stored successively in a storage means. CONSTITUTION:The fault detecting logic signals 2A-2D of fault detectors 1A- 1D are fed to storage devices 17A-17C. The device 17A stores the states of rise time signals 2A-2D when a storage controlling signal 16A is inverted to 1 from 0. At the same time, the devices 17B and 17C also store the states of the signals 2A-2D at their rise times when the corresponding storage controlling signals 16B and 16C are inverted to 1 from 0, respectively. Then the 1st, 2nd and 3rd stored fault state signals 19A1-19D1, 19A2-19D2 and 19A3-19D3 which correspond to the signals supplied from the devices 16A-16D, respectively are fed to an order deciding circuit 20. Thus the contents of the fault are decided first by the 1st signals 19A1-19D1 and then delivered to a display controlling circuit 21. In case the contents of fault are plural, the fault contents are sent to the circuit 21 based on the prescribed priority.

Fault discrimination system

Abstract: PURPOSE:To improve precision of fault discrimination by dispersing fault discriminating circuit to respective logical modules in a logical device, and holding fault information in each logical module. CONSTITUTION:In fault discriminating circuits I0-In, a latch group which holds respective fault detection signals in self-logical modules Y0-Yn or states of a group of signals is provided and the states of the latch groups in the circuits are frozen in the fault discriminating circuits I0-In of the logical module having generated fault detection signals respectively. Therefore, fault detection signals generated firstly in the logical modules Y0-Yn or a group of signals is discriminated by the state of the latch group.

Circuit arrangement for recording a fault current

Abstract: A fault current recording and processing arrangement is specified in which an integrated circuit (14) is used as a device for recording and evaluating a fault current signal produced by the secondary winding (12) of a summing current transformer (10). The device (14) is activated by means of additional elements (15, 90, 44, 63, 64, 82, 84, 90, 94, 96), by which means is provided chatter protection for a trip device (74), driven by a controllable semiconductor valve (54), and a neutral-line monitor, for both a.c. fault currents as well as d.c. fault currents.

Decentralized control type switching system

Abstract: PURPOSE:To shorten the time required for restart processing by transferring fault information to a processor for maintenance operation by providing a fault detecting means, which detects a fault including a switching processing fault, to every control processor, and also providing a means of instructing the start of an emergency program when detecting the switching processing fault by itself. CONSTITUTION:Channel networks 10, and 11-1n are equipped with subscriber circuits or trunks, and connected mutually through a junctor 2. A processor 7 for maintenance which controls the whole of switchboard is connected through a system bus 5 to processors 30, and 31-3n which exercise switching control over the channel networks 10, and 11-1n. This processor 7 is connected to fault detecting and fault processing program starting circuits 40, and 41-4n through a fault information transfer bus 6. Once the processors 30, and 31-3n detect faults of the channel networks 10, and 11-1n, emergency programs for the circuits 40, and 41-4n are started to transfer fault information to the processor 7, thus shortening restart processing time.

Vehicle battery charging circuit with fault indicator - monitors generator section including excitation as well as phase windings and rectifier diodes

Abstract: The vehicle battery charging system of the main patent includes a fault evaluating device (40) which can be in integrated circuit form This forms part of a system for indicating faults in the generator or mains supply etc, as well as the charge controller The generator section (10) includes a rectifier (13) with positive and negative diodes (13,13a) and a half bridge (14) with exciter diodes The fault evaluator is in the charge controller (16) with voltage and load regulator sections (17,18) The faults detected include too high or low generator output voltages, interruption of its excitation, and of the sensing line (46) connected to the positive connection point (B+) for the batteries, also interruption of the charging line (37), and of the generator Also faults in the region of the diodes (13) and the phase windings (12) of the generator are indicated PS

Fault Monitor for Multi-Megawatt Average Power Pulsers

Abstract: : Multi-megawatt average power repetitively operated pulsers using multiple switches requires fault protection to prevent damage to the pulser or its associated load. The pulser itself has to be protected against unequal current sharing through the multiple switches and against load or internal arcing. Furthermore, when a fault does occur, the fault protection must signal the system power supply to cease operation.

Automatic fault diagnosis of a switching regulator

Abstract: This paper describes a microprocessor-based system for the automatic fault diagnosis of a switching regulator. It covers the system from a test philosophy to a working breadboard that correctly identifies single simulated faults in the switching regulator. In addition to open circuit, short circuit, and stuck at faults, the system is capable of diagonosing faults due to excessive leakage, drift in critical components, and system instability.