Showing papers on "Fault indicator published in 1984"

Fault diagnostic distributed processing method and system

Abstract: In a distributed processing system having a plurality of interconnected subsystems of equal level, each subsystem operates to diagnose faults in other subsystems and protects its own subsystem based on the diagnosis of the faults of the other subsystems. The subsystems may be network control processors connected to common signal transmission lines, each of which carries major and minor loop check messages used to detect the faults in the other network control processors and constitutes a bypass route to protect its own unit when the fault occurs. If a transient fault occurs in the systems, an indication of the degree of the transient fault is stored and a possibility that the transient fault will change to a permanent fault is determined based on a time variation of the degree of the fault. If it is determined that the transient fault will change to a permanent fault, it is indicated to a man-machine system. In this manner, a loop transmission system which can be readily prediction-diagnosed for a fault is provided. In a second embodiment, means for calculating a feedback rate of a signal sent out to the transmission line and means for calculating the degree of fault on the transmission line based on the feedback rate calculated by the calculation means are provided.

Fault tolerant controller

Abstract: A controller operable in a normal mode of operation to control an output device in response to a sensed condition includes means for detecting a fault in the controller or output device. Means are responsive to the fault detecting means for controlling the output device in a failsafe mode of operation wherein the output device is safely operated without regard to the sensed condition when a fault is detected. Means responsive to the fault detecting means causes a return to the normal mode of operation only if the existence of the fault can be detected while in the failsafe mode and the fault ceases to exist during such time.

On a theory of t-fault diagnosable analog systems

Abstract: The theory of t -fault diagnosable systems initiated by Preparata et al. has been studied for applications to automatic self-testing of large scale digital systems. Recently, Amin introduced another variation of their model. In this paper, we show that this model has an application to analog fault diagnosis. We further specialize Amin's model to obtain characterization theorems which are much more transparent and also are more suitable for this particular application.

An analysis of the multiple fault detection capabilities of single stuck-at fault test sets

Abstract: Multiple fault detection using single stuck-at fault test sets is considered. The 74LS181 4-bit ALU is analyzed using 10 test sets varying widely in length and method of generation. The simulation results demonstrate significantly higher multiple fault coverage than anticipated by previous studies. It is shown that single stuck-at fault test sets can provide suitably high fault coverage for practical circuits with multiple outputs and reconvergent internal fanout.

System for detecting a program execution fault

Abstract: A system for detecting a fault in the program execution of a programmed digital signal processing system is disclosed. The fault detection system may include a plurality of monitoring devices for monitoring the execution of a plurality of program portions of the programmed processor and for generating a fault signal in response to a detected faulty program execution condition. Logic circuitry is included for restarting of suspending any fault signal generation rendered by the plurality of monitoring devices. Further included is circuitry for limiting the number of automatic restarts to a predetermined number which avoids continuous cycling between fault signal generation and reset. Still further, the predetermined number of fault generations must occur within a given time interval which may be set and from time to time changed by the program instructions, for example. A fault indication or alarm is not provided until the predetermined number of fault signal generations has occurred within the predetermined time interval. While in the alarm state, the monitoring devices are inhibited, rendering the fault detection system inoperative, and the program execution of the programmed processor is sustained in an initial state. The fault detection system further includes a power supply monitor which disables the logic circuitry when the power supply of the program processor is below a predetermined level to render the fault detection system inoperative and to sustain the program execution at its initial state.

Fault protection system for power supplies that use ferro-resonant transformers

Abstract: A fault detection system for use in power supply systems using ferro-resonant transformers is presented. Current sensing means are used to sense the current flowing in the ferro-resonant circuit associated with operation of the ferro-resonant transformer. A fault detection circuit, powered by its own power supply connected to the primary source of power, monitors the sensed current and signals any significant change therein. A fault condition in any of the secondary circuits of the transformer causes the ferro-resonant current to change, and upon sensing this change, the fault detection circuit disconnects the primary of the transformer from the source of power.

Fault Tolerance in Continuous Process Control

Abstract: Increasing the reliability of continuous process control systems means choosing a fault tolerance technique that matches computer hardware capabilities, as well as applications.

Fault simulation at the architectural level

Abstract: We have developed a method for fault simulation at the architectural level. This requires first an architectural level fault model. We have developed one based partially on the fault model proposed by Thatte and Abraham. An experiment with this fault model was done with a shift register described at both the architectural and gate levels. The resulting architectural level fault coverage tracked the gate level fault coverage obtained using the traditional stuck-at fault model. The next step was the development of an architectural level fault simulator, and an associated simulation model of the eight bit WE® 8000 microprocessor. The model was written in C, and 2512 faults were inserted in the model. A previously written test for the microprocessor was applied, and a fault coverage of 95% was obtained.

Process and device for determining a parameter associated with a faulty electric conductor, using a composite monitoring signal

Abstract: Method and apparatus for determining, at a measurement point in a faulty conductor of electrical energy, a fault parameter such as the distance between the point of measurement and such fault or the direction of such fault. As a signal of a fault current, the device utilizes a signal I pa formed by a linear combination of a signal representative of homopolar current and a signal representative of an inverse current associated with a fault. The invention is particularly applicable in the case of networks having at the point of measurement an insensitivity to homopolar current or to inverse current.

A Diagnosis Algorithm for the BGM System Level Fault Model

Abstract: A ?diagnosable system is a system in which all faults may be identified from the test results, provided that the number of faults does not exceed ?. In this correspondence we present an algorithm that may be used for the diagnosis of the system level BGM fault model proposed by Barsi, Grandoni, and Maestrini, whenever the system is ?-diagnosable and the number of faults is at most ?.

Sequential Fault Diagnosis of Modular Systems

Abstract: In this correspondence, we present an algorithm based on information theoretic concepts for the design of efficient sequential fault diagnosis experiments for permanent faults in modular systems.

Double seam tightness monitor

Abstract: This relates to a double seam tightness monitor wherein the second operation track of a cam of a double seaming apparatus or can closing machine is modified so as to permit the high dwell portion of the lobe thereof to deflect under loading from the associated cam follower which forces the second operation roll against the double seam component. Suitable strain gauges are associated with the deformable cam track portion and these are coupled in a bridge having a voltage output which is directed to a microprocessor. The microprocessor is provided with selected inputs which in combination with the voltage input from the bridge may be utilized to provide various signals including a high force condition signal, a pass condition signal, and a low force condition signal. There may also be associated with the microprocessor a printer for identifying the station where an abnormal condition exists, the specific force of the abnormal condition, the machine number, the time and the date. There may also be an output signal from the microprocessor which may be observed in several customary manners so as to permit a complete monitoring of the forces effected during the repeated seaming operations. There may also be a fault indicator for indicating when the same fault occurs at the same station repeatedly for a preset number of cans. The monitoring operation is entirely automatic except for the resetting of the fault indicator and for the manual control of the printing of high and low forces for those stations which are forming double seams that are passable. This abstract is not to be construed as limiting the claims of the application.

Functional testing of EPROMs

Abstract: The aim of this paper is to develop a testing scheme for EPROM memories. The starting point is the assumed general model of EPROM memory logic structure. For this model, an adequate fault model is developed. The class of faults taken into consideration includes faults in input-output buffers, faults in address decoding circuitry, and faults in memory cell arrays. The proposed testing scheme makes possible the detection of all faults included in the assumed fault model. This scheme takes into account technological and economic aspects. The method proposed is illustrated by detailed solutions for the 2716 EPROM memory.

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults

Abstract: Undetectable bridging faults between two arbitrary leads, which may produce feedback loops, in a unate two-level irredundant AND-OR network are anlyzed and their effect on stuck-at fault detection tests is explored. As a result, any complete test set for single stuck-at faults proves to still remain valid in the presence of undetectable bridging faults.

High-Resistance Grounding and Selective Ground Fault Protection for a Major Industrial Facility

Abstract: The high-resistance grounded system offers the distinct advantage of service continuity under single ground fault conditions which is critical to many industries such as petroleum, chemical, mining, textile, cement, pulp and paper, food, glass, utility, etc. A new major phosphate mine, with a total of 120 MVA electrical demand capacity, utilizes the high-resistance grounding method for the 480-V and 4160-V distribution systems. A complete ground fault protection scheme that includes both first fault alarm and second fault selective tripping protection was developed for the proper protection of the system. The design of this ground fault protection system has many unique features due to the complexity of the project. Design considerations including the system leakage current, the limitation of transient overvoltage, the grounding methods, the fault detection and annunciation, and selective isolation of faults based on circuit priorities, are analyzed.

Distributed processing system with fault diagnostic

Abstract: In a distributed processing system having a plurality of interconnected subsystems (1 - 5) of equal level, each subsystem has a function to diagnose faults in other subsystems and protects its own subsytems based on a result of the diagnosis of the faults of the other subsystems. The subsystems may be network control processors (100, 110, 200, 210,300, 310.400,410) connected to common signal transmission lines (1200, 2300, 3400, 4100, 1400, 2100, 3200, 4300), each of which sends out major and minor loop check messages to detect the faults in the other network control processors and constitutes a bypass route (100A, 110A, 200A, 210A, 300A. 310A, 400A, 410A) to protect its own unit when the fault occurs. An address train message for checking an address of the network control processor in the system can be transmitted and received as required. A tester (EXT 1010) for checking the system status is major unit of the present invention. If a transient fault occurs in the system, a degree of the transient fault is stored and a possibility of change of the transient fault to a permanent fault is determined based on a time variation of the degree of fault. If it is determined that the transient fault will change to the permanent fault, it is informed to a man-machine system to improve a maintenability. In this manner, a loop transmission system which can be readily prediction-diagnosed for the fault is provided. The second embodiment of the present invention includes means (7160) for calculating a feedback rate of a signal sent out to the transmission line and means (7320) for calculating the degree of fault on the transmission line based on the feedback rate calculated by the calculation means.

Fault indicator with magnetic test point

Abstract: Case 790429 FAULT INDICATOR WITH MAGNETIC TEST POINT Edmund O. Schweitzer, Jr. A fault indicator for use in conjunction with components of a power distribution system contained within a protective enclosure includes a magnetic test point on the exterior surface of the enclosure for indicating the occurrence of a fault in associated circuits of the system. The fault indicator includes a circuit module mounted on a conventional test-point provided on one of the system components, and a magnetic indicator module mounted on the wall of the enclosure. The indicator module includes a magnetizable element which extends through the wall of the housing to provide a magnetic test point. Upon occurrence of a fault in the system, circuitry within the indicator module energizes a first winding in the indicator module to establish a magnetic state of a first polarity at the test point. Upon restoration of power, a reset circuit energizes a second winding to establish a magnetic state of opposite polarity at the test point. A portable test instrument comprising a hand held housing on which a magnetized flag member is rotatably mounted is positioned adjacent the magnetic test point by a lineman to determine circuit status.

Stochastic fault analysis of balanced systems

Abstract: A sequence coordinates approach for fault calculations is extended to take into account the uncertainty of the network input data. The probability of a fault current on a bus exceeding its short circuit current is determined. These results would be of importance in determining the protective philosophy of any network. The simple 6-bus Saskatchewan Power Corporation System is used to demonstrate the features of this new development.

Short-circuit distance relay

Abstract: not available for EP0155367Abstract of corresponding document: US4755903In a short-circuit distance relay for protecting a single-channel power transmission system with power supplies installed at two ends thereof, when there exists any resistance at a fault point on the power transmission line, an error is induced in measurement of the distance up to the fault point by a voltage drop component flowing through the fault-point resistance from the remote-end power supply. In order to eliminate such error in measuring the distance, the relay of this invention computes the impedance up to the fault point from the information including a positive-phase voltage and a positive-phase current in a normal state of the power transmission system, and also a positive-phase voltage, a positive-phase current and a negative-phase current in a faulty state of the system, whereby the fault-point resistance is rendered unconcerned with the distance to consequently avert the measurement error.