Showing papers on "Fault indicator published in 1988"

A CMOS fault extractor for inductive fault analysis

Abstract: The inductive fault analysis (IFA) method is presented and a description is given of the CMOS fault extraction program FXT. The IFA philosophy is to consider the causes of faults (manufacturing defects) and then simulate these causes to find the faults that are likely to occur in a circuit. FXT automates IFA for a CMOS technology by generating a list of faults that are likely to occur in a CMOS circuit. The realistic faults generated by FXT are used to evaluate fault models, find the realistic fault coverage of test sets, and guide future testing research. How well various fault models characterize the realistic faults can be quantitatively measured because FXT's fault list includes the relative likelihood of occurrence (weight) of each extracted fault. The value of IFA and FXT is demonstrated by the analysis of five commercial CMOS circuits. This analysis shows that the traditional SSA fault model characterizes fewer than half of the faults extracted by FXT; graph-theoretic techniques provide little improvement in the percentage of realistic faults modeled. >

On the detection of delay faults

Abstract: The class of faults known as gate delay faults are investigated. A taxonomy of the classes of gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to detect gate delay faults are proposed. A physically meaningful measure to assess the efficacy of test sequences is introduced, and used to report fault coverages. A nine-valued logic system was proposed and used for deriving these tests. A physically meaningful measure, in the form of the average detection size of a test sequence. An algorithm was devised and implemented to automate the process of test generation, and results of experimentation with the ATPG, as well as with a random-pattern simulator, on four ISCAS-85 circuits were reported. >

A method of fault analysis for test generation and fault diagnosis

Abstract: The authors present a fault coverage analysis method for test generation and fault diagnosis of large combinational circuits. Input vectors are analyzed in pairs in two steps using a 16-valued logic system, GEMINI. Forward propagation is performed to determine, for each line in the network, the set of all possible values it can take if the network contains any single or multiple faults. Based on the values observed at primary outputs, backward implication is performed to determine the value actually carried by each line. Some deduced values imply the line is not faulty; similarly, some values imply that there is a fault in the subnetwork driving the line, or on the line itself. By keeping track of this information, it is possible to locate a fault to within its equivalence class. An extended fault model which includes stuck-at, stuck-open, and delay faults is used. Multiple faults of all multiplicities are implicitly considered; thus, the results obtained using this method are not invalidated in the presence of untested or untestable lines. >

Delay test generation. I. Concepts and coverage metrics

Abstract: An approach to test for delay faults is presented. A variable size delay fault model is used to represent these failures. The nominal gate delays with the manufacturing tolerances are an integral part of the model and are used in the propagation of simplified waveforms through the logic network. The faulty waveforms are functions of the variable-size delay fault. For each fault and test pattern, a threshold is computed such that this fault is detected if its size exceeds epsilon . This threshold is used (along with the minimum slack at the fault site) to determine a metric called quality. The quality of detection for a fault measures how close the test came to exposing the ideally smallest-size fault at that point. This metric (together with the traditional fault coverage) gives a complete measure of the goodness of the test. >

Detecting bridging faults with stuck-at test sets

Abstract: A method is described that provides high detection of bridging faults without requiring extensive fault simulation. Bridging fault coverage can be increased by doing fault simulation and test generation for bridging faults that are identified as hard to detect. These bridging faults occur between nodes that rarely, if ever, differ, or that seldom change value. In addition, if the nodes in the fault-free circuits toggle often, feedback faults are easier to detect. This is true even if the nodes involved always have equal values. Methods for identifying such nodes have been presented. These methods use results available from fault-free simulations. A simple solution is to randomly reorder the test vectors to increase toggling and therefore increase bridging fault coverage. As a result, computer time for test generation will be only slightly greater than the time required for stuck-at fault generation alone. >

On-line hazard aversion and fault diagnosis in chemical processes: the digraph+fault-tree method

Abstract: A method for online hazard aversion and fault diagnosis in chemical processes is developed. The method uses a directed graph model of process operation and control. Fault trees developed from the directed graphs are combined with real-time data to provide online diagnosis for hazard aversion and fault detection. Both hardwired control and manual control are modeled. A single control loop illustrates the modeling technique and the diagnosis method. The method provides an advance alert to process problems and an identification of the problems' causes, based on the available real-time data and prior rates of equipment malfunctions and process disturbances. >

Application of adaptive Kalman filtering in fault classification, distance protection, and fault location using microprocessors

Abstract: An adaptive Kalman filtering scheme is presented for estimation of the 60 Hz phasor quantities, fault type identification, distance protection, and fault location. The current and voltage data of each phase are simultaneously processed in two Kalman filter models. One model assumes that the phase is unfaulted, while the other model assumes the features of a faulted phase. The condition of the phase is then decided from the computed a posteriori probabilities. Upon the secure identification of the condition of the phase, the corresponding Kalman filtering model continues to obtain the best estimates of the current or voltage state variables. Upon convergence to highly accurate values, the appropriate current and voltage pairs are selected to decide the zone of the fault and the fault location. The scheme was tested on digitally simulated data. The fault classification was doubly secure using both voltage and current data. The convergence of estimates reached exact values within half a cycle. >

Algorithm comparison for high impedance fault detection based on staged fault test

Abstract: Four high-impedance fault-detection algorithms-proportional relaying, ratio ground relaying, second-order harmonic current relaying, and third-order harmonic current relaying-were simulated by mathematical models. Relaying performances using staged fault data were then compared. Results of the fault data processing were used to distinguish the detection characteristics: fault identification, stability, threshold setting adaptability, transient recovery characteristic, and availability. The operations of a ground overcurrent relay and a ratio ground relay were also checked in the test. The results can be used as a reference for the development of a reliable high-impedance fault detector. >

Fault capture/fault injection system

Abstract: Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.

Diagnosing multiple faults using knowledge about malfunctioning behavior

Abstract: A technical fault diagnosis system based on knowledge about the structure of a device and the behavior of its components is presented. This approach allows knowledge about components to be reused for new devices and simplifies maintenance of the fault diagnosis system. A new method for diagnosing multiple faults using this representation is presented and discussed. The method assumes that both normal functioning and malfunctioning behavior are described for components in the form of user-defined constraints. A prototype implementation for parts of the method exists and has been compared with a traditional fault-tree implementation of a trouble-shooting system for an separator application.

Testing for multiple faults in domino-CMOS logic circuits

Abstract: The problem of multiple faults detection in domino-CMOS logic circuits is considered. The multiple faults can be of the stuck-open and stuck-on types. It is shown that a multiple fault in the domino-CMOS circuit can be mapped to a multiple stuck-at fault in its gate-level model. A method is given to initialize the domino-CMOS circuit and apply a multiple stuck-at fault test set based on the gate-level model of the circuit. This results in the detection of all multiple faults having detectable consistent faults. The problem of test set invalidation due to arbitrary signal delays is easily taken care of in domino-CMOS circuits, making such an implementation of a function even more attractive than a fully complementary CMOS implementation, from the testability point of view. >

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits

Abstract: An exact fault simulation can be achieved by simulating only the faults on reconvergent fanout stems, while determining the detectability of faults on other lines by critical path tracing within fanout-free regions. The authors have delimited, for every convergent fanout stem, a region of the circuit outside of which the stem fault does not have to be simulated. Lines on the boundary of such a stem region, called exit lines, have the following property: if the stem fault is detected at the line, and the line is critical with respect to a primary output, then the stem fault is detected at the primary output. Any fault-simulation technique can be used to simulate the stem fault within its stem region. The fault simulation complexity of a circuit is shown to be directly related to the number and size of stem regions in the circuit. Results obtained for the well-known benchmark circuits are presented. >

Transmission line fault location using digital fault recorders

Abstract: A technique for the location of transmission line faults using voltage and current measurements from one end of the faulted line is presented. The method differs from past approaches in that a time domain rather than a frequency domain representation of voltage and current is used. A phase network model is used, permitting explicit treatment of self and mutual impedance effects for either a single three-phase circuit or two parallel three-phase circuits. The algorithm will be used as one of the analysis functions for a digital fault recorder. Test results are presented to illustrate the performance of the algorithm under various system conditions and configurations. Results compare favorably with those obtained using previously reported fault location methods. Estimated fault locations are within 3 to 4% of the actual fault location. Most cases show errors within 2% of the actual fault location. >

Multiple stuck-open fault detection in CMOS logic circuits

Abstract: It is shown that a test set based on two-pattern tests, which are designed to detect single stuck-open faults, can be found that detects all multiple stuck-open faults inside any CMOS gate in the circuit. The concept is extended to three-pattern tests, which are obtained for every single stuck-open fault at the checkpoints. If a certain condition is satisfied, then it can be shown that the resulting test set can detect any multiple stuck-open fault in the circuit. Even when this condition is not fully met, a very large percentage of the multiple stuck-open faults can still be guaranteed to be detected. For the special case of fan-out-free CMOS circuits, it is shown that a single stuck-open fault test set based on two-pattern tests can always be found that has 100% multiple stuck-open fault coverage. This test can also be guaranteed to be robust in the presence of arbitrary delays. >

Incipient Fault Detection In DC Machines Using A Neural Network

Abstract: Rotating machines are used extensively to convert electrical energy to mechanical energy. In this paper, an incipient fault detection scheme using a neural network is presented. An incipient fault within a motor usually affects its performance. Factors such as conductive contamination, loose hardware, design defects, worn bearings, abnormal operation, aging and disturbance can cause damage to the motor. The symptoms of the faults are usually reflected by changes in parameter values and the steady-state operating condition of the motor. The neural network is basically a software (or hardware) implementation of parallel computing which identifies different input patterns and generates appropriate outputs. Data is collected on the parameters and state values of the motor under different fault conditions. Based on these data, a neural network is then implemented to perform incipient fault detection.

Digital signal fault detector

Abstract: The present invention comprises an electrical test circuit for testing a signal in a digital circuit, to detect common analog signal deficiencies or "faults". More specifically, the test circuit can simultaneously detect one or all of three such faults in a digital circuit, including: (1) a voltage spike which occurs when the signal briefly jumps either high or low; (2) a float fault which occurs when the signal is floating for too long; and (3) a noise fault which occurs when the signal passes from either the high or the low state to the float state, and then returns directly to the same state. The signal to be tested is first processed in an input state discriminator to classify it by state, either high, low, or float. In a preferred embodiment, both the high voltage threshold and the low voltage threshold of the input state discriminator are adjustable separately to accommodate all logic families. Following classification, three circuits test simultaneously for the appearance of the three separate faults, each circuit testing for a different fault. The spike fault circuit and the float fault circuit each include an adjustable timer, logic, and a comparator to test for the respective fault. The noise fault circuit includes logic to test for a noise fault. Thus, the present invention is adaptable for testing virtually any digital circuit, operating asynchronously or at any of a wide variety of frequencies. The present invention can be used alone as a device to verify proper digital circuit operation, or it can be used in combination with another testing device such as a logic analyzer.

A fault simulation method based on stem regions

Abstract: The concept of stem regions has been used as a framework for a fast fault simulator for combinational circuits. The concept allows a static reduction of the circuit area of explicit analysis, for single-output as well as multiple-output circuits. A dynamic reduction of processing steps is also achieved as the fault simulation progresses and fault coverage increases. Both the static and dynamic reductions are fully compatible with the parallel pattern evaluation technique, resulting in a very efficient implementation. The simulation algorithm is described, and experimental results for well-known benchmark circuits are shown. >

Power control and fault isolation indicator

Abstract: A power supply system, which supplies a number of different A.C. and D.C. voltage levels to a plurality of loads, is monitored at a number of points for undervoltage, overvoltage and/or overcurrent fault conditions. A diagnostics logic circuit, which is formed from relatively inexpensive, readily available logic units, generates a BCD code signal indicating a fault in response to the occurrence of a fault condition at one of the monitored points. The system responds to this BCD fault indicating code signal by, on the one hand, protecting the power system by actuating a main relay to open the A.C. power line to the system and generating a shutdown signal applied to a pulse width modulator of a converter in the system and, on the other hand, by driving a seven-segment display which displays a numeral to indicate the location of the fault condition. In order to avoid false undervoltage fault signals while the system voltages are coming up after the system is turned on, a delay circuit is used to mask the BCD code generating portion of the diagnostics logic until the system voltages reach normal operating levels.

Fault indicator having electrostatically-actuated indicator flag

Abstract: A fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrostatically-actuated indicator assembly. During normal operation a lightweight indicator flag rotatably mounted in and viewable from the exterior of the indicator housing is held in a reset-indicating position by electrostatic force resulting from an electric field existing between the flag and adjacent electrodes. Upon occurrence of a fault current in the monitored conductor the electric field is removed and the indicator flag, under the influence of a permanent magnet, is caused to rotate to a fault-indicating position. By avoiding the use of magnetic actuator windings and associated pole pieces the indicator assembly is easier and more economical to construct.

Deriving fault location and control from a functional model

Abstract: It has been established that, by directly representing a system's components and their interactions, causal models lead to algorithmic methods for the monitoring, diagnosis, and control of fault recovery. Analysis of sensor data with component-oriented models has demonstrated that: (1) sensor failure is easily identified, (2) the absence or degradation of sensor data is easily accommodated once recognized, and (3) emergency signals and warnings can be intelligently selected or generated from the same system description. Control steps can also be dynamically derived, permitting the automation of state maintenance and failure recovery. An implementation (the KATE system) of the ideas presented is discussed. >

Add-on ground fault module

Abstract: Ground fault detectors commonly interconnect secondary windings of the phase current transformers of a source (N1, N2, N3) into a summing circuit. This circuit will produce a zero output when there is no ground fault condition and will produce on a non-zero output if a ground fault condition exists. A problem exists in that a ground fault detector is not easily connected to an existing system. A solution to this problem is an add-on ground fault system including a module (10) readily connected to the distribution line (N4, N5, N6) and to the associated breaker (STS).

New algorithm for distance protection of high voltage transmission lines

Abstract: Calculated reactance between relay point and fault represents an accurate estimation of fault distance when the fault resistance or the R/L ratios of the equivalent impedance at line ends are very small. When these conditions are not satisfied, a large error results in locating fault distance due to back-feed effect from the remote end. A new recursive algorithm for distance protection is developed, which accurately determines the fault location by predicting the back-feed current. The prediction needs estimated values of the remote end source impedance to be passed to the relay via a communication link. Trip decision is based on checking the evaluated fault location and its variation with time. The algorithm is validated by digitally simulating transmission lines with different fault conditions taking into consideration the reduction in the generator reactance after fault inception. Simulation results show a fault detection time of about one half-cycle.

Test generation for sequential circuits using individual initial value propagation

Abstract: Describes a test generation and fault simulation method which detects faults in the clock control logic that can cause register initialization failure in sequential circuits. By assigning an individual initial value X/sub n/ to the inaccessible register n in the faulty circuit and observing both the fault signal 0/X/sub n/ (0 in the good circuit/X/sub n/ in the faulty circuit) and 1/X/sub n/ in a different time frame, test vectors which can detect previously undetectable faults can be generated. Consequently, this method can generate test vectors with 98% to 100% fault coverage for sequential circuits for which conventional test generation methods only achieve 89% to 95% coverage. >

Protection device for high resistance ground faults

Abstract: Protection device for high resistance ground faults in a power network the fault detection principle of which is based on an indirect study of non-harmonic frequency compo­nents of the phase currents. When such a fault has occurred, a considerable change of the energy contents of these fre­quency current components arises. This change can be de­tected by the device according to the invention. If by com­parison (4e) between digitized input signals (I′) and a har­monic Fourier model (4d) of the same signals, i.e. genera­tion of the residuals of the system, it is found that a dif­ference exists, and if the corresponding loss function VN (4f) for a certain time exceeds a lower limit value - all on condition that a zero sequence current (IO) exists - then the device indicates a high resistance ground fault on any of the phases of the network.

Fault section locating apparatus

Abstract: Unit switches 21 are arranged at respective load points of a power feeding bus 3 in a ring-like distribution network. Each of the unit switches comprises, besides three switch means 18, 19, 20, drive means operating in response to short- circuit faults and ground faults found by current transformers 11X, 11Y and a zero-phase-sequence current transformer 6 inserted in the bus, and a fault indicator 10 which is actuated by the drive means. Thus, a faulty section is determined on the basis of the presence of operated fault indicators at the load points.

Fault diagnosis in combinational digital circuits using a backtrack algorithm to generate fault location hypotheses

Abstract: A backtrack algorithm for the generation of fault location hypotheses in combinational digital circuits is presented. The algorithm uses the results of applied tests and works back from incorrect circuit outputs to generate a list of possible single and/or multiple faults. Suggestions are given for refining the list by selecting probing measurements and by computing the intersection of more than one list resulting from multiple tests.

Fault diagnosis under a limited-fault assumption and limited test-point availability

Abstract: This paper describes a method of fault diagnosis for large interconnected circuits in which the number of faults is limited to, say,nf where it is possible thatnf exceeds the number of output measurements,no. The problem and its solution are formulated in the context of a frequency domain tableau based on the component connection model of a circuit/system. The paper describes Jacobian tests for diagnosability whennf≥no and states a full parameter diagnosability test as a corollary to the main theorem. An algorithm is developed for the identification of faulty parameters in this limited fault case. Finally, examples, including a 26-parameter video-amplifier circuit, illustrating the technique are given.

Trigger circuit for a device for protecting occupants of a vehicle

Abstract: A trigger circuit for a device for protecting occupants of motor vehicles is described, having an acceleration sensor for outputting a signal which corresponds to the deceleration of the motor vehicle in the event of an impact against an obstacle, having an evaluation circuit which evaluates the output signal of the acceleration sensor, a switch which, starting from a specific value (trigger value) of the output signal of the evaluation circuit, triggers the safety device by means of a firing element, and with a self-diagnostic function for the trigger circuit with a data transmission device for outputting status information on the status of the trigger circuit and a data receiver which is connected to a fault indicator and to an intelligent interface, data pulses being sent via a signal line which is identical to the power supply line of the trigger circuit.