Showing papers on "Fault indicator published in 1989"

Incipient fault diagnosis of chemical processes via artificial neural networks

Abstract: Artificial neural networks have capacity to learn and store information about process faults via associative memory, and thus have an associative diagnostic ability with respect to faults that occur in a process. Knowledge of the faults to be learned by the network evolves from sets of data, namely values of steady-state process variables collected under normal operating condition and those collected under faulty conditions, together with information about the degree of the faults and their causes. Here, we describe how to apply artificial neural networks to fault diagnosis. A suitable two-stage multilayer neural network is proposed as the network to be used for diagnosis. The first stage of the network discriminates between the causes of faults when fed the noisy process measurements. Once the fault is identified, the second stage of the network estimates the degree of the fault. Thus, the diagnosis of incipient faults becomes possible.

A hybrid expert system for faulted section identification, fault type classification and selection of fault location algorithms

Abstract: This paper presents an expert system developed in turbo prolog to identify faulted sections and interpret protective apparatus operation in large interconnected power systems. The expert system presented here is capable of identifying bus faults, line fault sections, and fault sections in the common area of a specific bus and line. Also, the expert system identifies relays or breakers malfunctions. The expert system is then expanded to include real-time measurements of current and voltage phasors to classify the type of fault that the faulted section has experienced. Furthermore, when the faulted section is a transmission line, the expert system selects an appropriate fault location algorithm to compute the fault location in miles. This paper shows that the combination of numeric and data base algorithm is essential to many developments in expert system application in power systems. Evaluating the expert systems reported so far for fault diagnosis reveals that all of these schemes utilize only the data received from breaker and relay status. Consider the recent trend in digital protection, real-time phasor measurements would be available. To combine real-time phasor measurements with relay and breaker status, a hybrid expert system is required. A hybrid expert system combines numeric algorithms with data base algorithms in one scheme. This paper recognizes this feature in the expert system developed here. The expert system reported in this paper includes four stages. The first stage determines the faulted section of the power system and reports correct and incorrect breaker and relay operation.

Parallel Pattern Fault Simulation of Path Delay Faults

Abstract: This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.

On the computation of the ranges of detected delay fault sizes

Abstract: Existing methodologies for determining gate delay fault coverages through the computation of detected fault sizes are shown to have certain deficiencies A method is proposed to determine all the possible ranges of detected fault sizes, thereby maximizing the fault coverage of a given test sequence The ultimate goal of ensuring that the coverage for a particular fault extends up to the actual circuit slack is explored, and methods are given to achieve such coverages wherever possible Results of experiments performed to evaluate the practical benefits of the proposed methods are reported >

Fault location method for radial transmission and distribution systems

Abstract: A method of locating a phase-to-ground fault in a radial distribution system with a tapped load. The method includes determining the positive-sequence impedance from the residual current, the residual current compensation factor and the phase-to-ground voltage of the faulted line. The positive-sequence impedance is then used to determine the distance to the fault.

Fault diagnosis in analogue circuits using AI techniques

Abstract: The authors describe a technique for detecting and locating faults in analogue circuits by checking that the measurements are consistent with the circuit function. The unique representation used accommodates the imprecise nature of analogue circuits. A model of the circuit is formed from the constraints imposed by the behavior of the components and the interconnections. The values of parameters within the circuit are deduced by propagating the effects of measurements through this model. Faults are implied from the detection of inconsistencies and located by suspending constraints within the model. The method does not use fault simulation and is therefore applicable to any type of fault. It is able to detect performance variations, as well as catastrophic failures. Values are represented as ranges within which the true value lies. This overcomes the difficulty of representing the uncertainty inherent in any analogue design or measurements. The method has been successfully used to detect and locate a number of faults in several circuits. >

Unpredictable fault detection using adaptive inference testing techniques

Abstract: A method of using an adaptive inference system to detect and locate faults in an electrical or electronic device or assembly. A position-dependent, time-ordered test is performed upon the device or assembly to provide a comprehensive error analysis. The error analysis includes an array of error data and information that is time interdependent. Once fault data is stored in memory, a newly-detected fault can be compared with the stored faults. A relationship between the stored fault data and the detected fault is determined. The system indicates the cause of the detected fault to the operator based on stored fault data that is most probably related to the detected fault. Possibilites of faults within the device or assembly are then displayed. This system analysis and range of potential causes can be evaluated by an operator. In this manner, faults not having been contemplated by stored data and information in the adaptive inference system and not bearing a direct relationship to a problem being reviewed can be identified.

Current adaptive fault indicator

Abstract: The disclosed fault indicator which senses current in a cable, resets in response to a minimum current and arms a trip arrangement in response to current rising a predetermined amount with respect to time. If the rising current also opens a circuit breaker within a predetermined time and cuts off current to the cable, the indicator trips. If no zero current occurs within the time period, the trip arrangement is disarmed for the next current rise.

The parallel-test-detect fault simulation algorithm

Abstract: It is shown how the test-detect principle can be adapted to the parallel-patterns technique for combinational fault simulation. Several techniques for implementing a parallel-test-detect simulator are presented, with techniques based on nominator analysis providing the fastest fault simulation results. The dominant-test-detect approach has proved to be effective both for small sets of patterns, as might be used in automatic test pattern generation, and for larger pattern sets that might be used in built-in self-test. >

Apparatus for detecting faults on power transmission lines

Abstract: In a system for transmitting an electrical power supply by means of an over-head power transmission line supported by power transmission towers, a fault such as a short-circuit fault and a ground fault is detected by providing optical current sensors having opto-magnetic elements and opto-electric field elements on respective conductors of the transmission line to detect a fault current and fault voltage on the basis of the Faraday's effect and Pockel's effect. Light beams passing through the elements are modulated by the magnetic fields induced by the currents passing through the conductors and the voltages on the conductors, and thus include information about the current and voltage. There is further provided a circuit for calculating a distance to a fault point in accordance with the detected current, voltage and a phase difference therebetween and a known impedance of the power transmission line. The thus calculated distance to the fault point is displayed on display means which is arranged at the power transmission tower or the substation.

A Simplified Six-Waveform Type Method for Delay Fault Testing

Abstract: A new, simplified waveform method is presented for delay fault testing. The method enables accurate calculation of a delay fault detection threshold for definitely detectable faults, and a delay fault range for possibly detectable faults. The method is shown to correctly classify definitely detectable faults which are mis-classified by methods recently reported elsewhere [1] [2]. A quantitative delay fault model with variable fault size is used, and the effect of the delay fault is explicitly described by the new waveform method. The calculation of the detectable delay size threshold occurs in linear time for any definitely detectable fault.

High impedance fault detection for industrial power systems

Abstract: The authors describe the characteristics of high-impedance faults and the most effective techniques for detecting them. The benefits of high-impedance fault detection for industrial power systems are identified. It is shown that the most effective high-impedance-fault detection system incorporates several algorithms and monitors a number of parameters to ensure sensitivity and correct operation. Operating the detector in an alarm mode improves safety and fault location with minimal effect on service continuity. A valuable use for such a detector would be the identification of incipient faults, so that critical loads can be switched to another source before the fault becomes bolted and requires the circuit to be cleared. Using a detector in this way could save substantial down-time costs for critical processes. >

Transient and intermittent fault insertion

Abstract: Fault insertion circuits under programmable control and resident in an integrated circuit (LSI or VLSI) (10) insert transient and intermittent fault classes in addition to a permanent fault class into functional logic (24) on such integrated circuit (10). Specific fault types programmable for each fault class include a stuck-open fault and bridging faults both wired-AND and wired-OR. The programmable fault insertion circuitry on each integrated circuit interfaces directly or indirectly with a BIT maintenance controller (12). In addition to verifying test software, a fault tolerant system's error detection and recovery circuits may be verified by fault insertion testing using the transient and intermittent fault insertions. The controller (12) inserts a fault (11) into the integrated circuit (10) with control and initialisation data words and monitors the effect of the fault on the functional logic (24). The fault control and initialisation data words are stored in timers (52, 54, 56), a fault word register (14), and an intermittent fault mode logic (60), and are decoded under the control of the controller (12) and a slaved timing and control generator (17) to load a fault type generator (16) which responds by supplying a fault type signal (FAULTn) to a fault insertion interface (18) which thereupon inserts the required fault into functional logic (24) by appropriate modification of the coupling between an output signal (N) from and and an input signal FSIGNAL(N) to the functional logic (24).

A Deterministic Approach to Adjacency Testing for Delay Faults

Abstract: Adjacency testing for delay faults is examined in both theory and implementation. We shall show that the necessary and sufficient conditions for adjacency testability yield an efficient method of robust delay test generation. Empirical results (including several different cost measurements) are presented which demonstrate that our technique: (1) achieves high fault coverages under both the robust and nonrobust delay fault models and (2) is cost effective.

Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits

Abstract: A methodology relating physical defects to the circuit-level faulty behavior caused by these defects and a fast algebraic implementation to provide a realistic fault list are proposed. In conjunction with the obtained statistical data on the likelihood of each fault and the knowledge of its best observable electrical manifestation, a solid basis for an effective and powerful test pattern generation is provided. To achieve an accurate modeling of bridging faults, a novel fault model, the large-scope short, is developed and implemented. In contrast to other fault analysis procedures which use time-consuming simulation methods to generate or induce physical defects, the proposed Fantestic methodology is very fast in extracting defects and converting them to a ranked fault list. The analysis of some sample CMOS circuits illustrates the effect of different physical defects on circuit-level faults. >

Smart power driver system for a motor vehicle

Abstract: An electrical power driver system with fault monitoring provision for both a self test mode and a normal operating mode. During the self test mode, the power driver is momentarily actuated during test intervals and its output compared to a predetermined value for providing self test fault indications. Each power driver is sampled and an indication provided of whether the fault is new or old in addition to providing a count of faults. During normal operation, monitoring circuitry provides indications of a plurality of fault types including over temperature, open circuit, short to ground, and short to voltage. A determination is made of whether each fault type is new or old and a count of faults provided. Output formatting provides indications of fault type, fault count, and whether the fault is intermittent or hard.

Method of fault protection for a microcomputer system

Abstract: The present invention is a method of fault protection for a microcomputer system. The method determines whether the system returns to a normal or special operating mode if a fault is detected by determining the microprocessor's past history before the fault occurred thereby allowing the microprocessor to get back on track in an appropriate manner.

New fault location system for power transmission lines using composite fiber-optic overhead ground wire (OPGW)

Abstract: This paper describes a new method of locating the section where an electrical fault occurs on a power transmission line using Composite Fiber-Optic Overhead Ground Wires (OPGWs). This fault location (FL) method locates the fault section by measuring the current induced in the ground wire (GW), i.e., OPGW in this system. The OPGW currents are measured at many towers which divide the power line into sections. Data is transmitted to a central monitoring station as an optical signal through the optical fibers included within OPGW. Prior to the development of this new FL system, a simulation of power line faults using Electro-Magnetic Transients Program (EMTP) was conducted. As a result, the following two points were clarified; 1) Since OPGW current changes with line condition, it is quite difficult to define a fixed threshold level to locate fault sections accurately. 2) The distribution pattern of OPGW current along the power line has clear features around the fault point, so it is possible for electric power engineers to find the fault section by relative comparison. Therefore, the FL algorithm to be developed should have the capability of finding out the fault section with a human-like method of recognition. Fuzzy Theory, an attempt to include this kind of humanlike way of thinking into computers, was investigated and a new FL method applying this theory was developed. Fig. 1 shows the OPGW current distribution pattern of a typical grounding fault calculated by EMTP as an example.

Test Pattern Generation for Stuck-Open Faults Using Stuck-At Test Sets in CMOS Combinational Circuits

Abstract: In this paper we investigate two aspects regarding the detection of stuck-open (SOP) faults using stuck-at test sets. First, we measure the SOP fault coverage of stuck-at test sets for various CMOS combinational circuits. The SOP fault coverage is compared with that of random pattern test sets. Second, we propose a method to improve the SOP fault coverage of stuck-at test sets by organizing the test sequence of stuck-at test sets. The performance of the proposed method is compared with that of a competing method. Experimental results show that the proposed method leads to smaller test sets and shorter processing time while achieving high SOP fault coverage.

Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model

Abstract: Limitations in current testability approaches have forced major compromises in IC fault modeling, test, and quality. The stuck-at fault model is inadequate to achieve very high quality. Meaningful CMOS fault models based on schematically extracted faults are presented. Unity observability, the ability to probe all nodes, is presented as a practical approach to effective use of these models

Plant diagnostic apparatus

Abstract: According to a plant diagnostic apparatus of the present invention, a simulation fault value of the case that an estimated fault occurs is displayed on the screen and therefore diagnostic probability of true-or-false of displayed cause of the fault can be improved. Moreover, since an estimated fault, a simulation value of the case that an estimated fault progresses and a normal period simulation value of the case that no fault occurs are displayed on the same screen, a simulation value of the estimated fault and normal value can be compared for judgement and thereby diagnostic probability of true-or-false decision of the estimated fault can be improved. In addition, since an estimated fault, a simulation value due to the estimated fault and a simulation value of the case that a measure is taken for the estimated fault are displayed on the same screen, probability of true-or-false decision of the estimated fault can be improved by comparing these values.

System for detecting and limiting electrical ground faults within electrical devices

Abstract: An electrical ground fault detection and limitation system for employment with a nuclear reactor utilizing a liquid metal coolant. Elongate electromagnetic pumps submerged within the liquid metal coolant and electrical support equipment experiencing an insulation breakdown occasion the development of electrical ground fault current. Without some form of detection and control, these currents may build to damaging power levels to expose the pump drive components to liquid metal coolant such as sodium with resultant undesirable secondary effects. Such electrical ground fault currents are detected and controlled through the employment of an isolated power input to the pumps and with the use of a ground fault control conductor providing a direct return path from the affected components to the power source. By incorporating a resistance arrangement with the ground fault control conductor, the amount of fault current permitted to flow may be regulated to the extent that the reactor may remain in operation until maintenance may be performed, notwithstanding the existence of the fault. Monitors such as synchronous demodulators may be employed to identify and evaluate fault currents for each phase of a polyphase power, and control input to the submerged pump and associated support equipment.

Fault current protection device

Abstract: Fault current protection device, in which a first subordinate device, which acts as a fault-current circuit-breaker, for protecting against fault currents of a first type, is combined with a second subordinate device, which acts as a residual-current circuit-breaker, for protecting against fault currents of a second type. According to the invention, it is provided that the first subordinate device (1), fault-current circuit-breaker, is designed in such a way that it reacts at least to a.c. fault currents, and that the second subordinate device (2), residual-current circuit-breaker, is designed to react to fault currents from direct current, alternating current and pulsating fault currents, and that the sensitivity of its triggering is matched to the earth-leakage circuit-breaker in such a way that the triggering in the case of a.c. fault current and in the case of pulsating fault currents lies essentially above that of the fault-current circuit-breaker, and the triggering in the case of fault currents from smooth direct current corresponds to the sensitivity of the fault-current circuit-breaker in the case of a.c. fault current or in the case of pulsating fault currents.

Fault monitoring device and control method for information processing system

Abstract: PURPOSE: To monitor and recover the fault of a computer system from a remote place by providing a computer system as the controlled object with a monitor controller. CONSTITUTION: An information processing system 250 as the monitored object relays the data line, through which message data is sent to a conventional master console 102, and monitors message data. With respect to detection of hardware fault, a private interface line is provided between a central processing unit 200 and the system to detect the occurrence of fault or gather fault information. Consequently, it is unnecessary to change a conventional operating system, and the malfunction is prevented. Thus, fault monitor and recovery of the information processing system, namely, the computer system are performed from a remote place. COPYRIGHT: (C)1991,JPO&Japio

A fault model for PLAs

Abstract: A fault model for programmable logic arrays (PLAs) is discussed that handles four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that a test that detects all multiple crosspoint faults also detects all multiple stuck-at faults, multiple bridging faults, and any combination of the above. It is also shown that multiple faults form a substantial part of the set of all faults in PLAs. Experiments with test generators show that tests detecting all single testable crosspoint faults also detect all testable stuck-at faults. The experiments also show that the test strategies based on the single-crosspoint fault model cover the greater part of all faults in PLAs. >

Fault indicator with inrush restraint

Abstract: An inrush restraint in a fault indicator disables trip in response to the current in the cable being monitored changing from reset to trip values within a predetermined period.

Exact critical path tracing fault simulation on massively parallel processor AAP2

Abstract: A fault simulation method called the fault information tracing (FIT) algorithm is presented. Although the basic concept is similar to that of the critical path tracing (CPT) method, which traces sensitive inputs backward to directly determine the fault detectability, FIT is a multiple fault propagation method which considers propagation of all possible stuck-at faults between a gate input and output. Moreover, FIT manages a 'fault information flag' which represents both fault detectability and circuit topology between the current line and a primary output. Use of the fault information flag makes it possible to greatly reduce reconvergent fanout stem analysis. Consequently, exact and efficient simulation is achieved with near linear time complexity. The FIT algorithm is described and results are presented. In addition, the FIT procedure consists of simple propagation of fault information flags between logic gates, which enable implementation on parallel processors. Its suitability for parallel processors. Its suitability for parallel processing is discussed. Moreover, a parallel fault simulation method for AAP2, a massively parallel processor system containing 65536 processing elements, is described. >

Liquid crystal electrical fault indicators

Abstract: An electrical apparatus having a liquid crystal fault indicator, comprising: an electrical component subject to electrical fault; a smectic liquid crystal display having an indicating element having a first and a second visual state, said indicating element being capable of transitioning from the first to the second visual state upon the application of an electric field sufficient to realign the smectic liquid crystal material contained therein and remaining in the second visual state after the removal of the electric field and further being capable of transitioning from the second to the first visual state upon heating to at least a delatching temperature Td sufficient to destroy the electric field induced alignment of the smectic liquid crystals; and fault signal means for providing, upon the occurrence of a fault, a prescribed input sufficient to cause said indicating element to transition from a visual state indicative of an unfaulted condition to a visual state indicative of a faulted condition.

Simultaneous fault simulation using the generalized method of fault analysis

Abstract: The author describes a procedure for simultaneous fault calculations using the generalized method of fault analysis. This approach, which can handle various faults without any restrictions on fault types, total numbers, or location, serves as the foundation of new fault analysis programs which are replacing the traditional short-circuit programs at various utility companies. The fundamental difference between this method and the tradition symmetrical component method is that faults are simulated on a phase network rather than on the sequence network. This gives the new technique additional flexibility in terms of simulating faults on different phases. >