Showing papers on "Fault indicator published in 1992"

Investigation of fault modes of voltage-fed inverter system for induction motor drive

Abstract: The reliability of power electronics systems is of paramount importance in industrial, commercial, aerospace, and military applications. The knowledge about the fault mode behavior of a converter system is extremely important from the standpoint of improved system design, protection, and fault tolerant control. This paper describes a systematic investigation into the various fault modes of a voltage-fed PWM inverter system for induction motor drives. After identifying all the fault modes, a preliminary mathematical analysis has been made for the key fault types, namely, input supply single line to ground fault, rectifier diode short circuit, inverter transistor base drive open, and inverter transistor short-circuit conditions. The predicted fault performances are then substantiated by simulation study. The study has been used to determine stresses in power circuit components and to evaluate satisfactory post-fault steady-state operating regions. The results are equally useful for better protection system design and easy fault diagnosis. They will be used to improve system reliability by using fault tolerant control. >

A new fault location technique for two- and three-terminal lines

Abstract: A method for the computation of fault location in two- and three-terminal high voltage lines is presented. It is based on digital computation of the three-phase current and voltage 60/50 Hz phasors at the line terminals. The method is independent of fault type and insensitive to source impedance variation or fault resistance. Furthermore, it considers the synchronization errors in sampling the current and voltage waveforms at the different line terminals. The method can be used online following the operation of digital relays or offline using data transferred to a central processor from digital transient recording apparatus. The authors start with a two-terminal line to explain the principles and then present the technique for a three-terminal line. The technique was first tested using data obtained from a steady-state fault analysis program to evaluate the convergence, observability, and uniqueness of the solution. The technique was then tested using EMPT-generated transient data. The test results show the high accuracy of the technique. >

Method and system for diagnosis and analysis of products troubles

Abstract: A computer-implemented method and system for diagnosing and system for diagnosing and analyzing fault information of a product is carried out by (a) creating a fault tree representing causal relations between faults and causes thereof base on information of past faults and information concerning the structure and characteristics of the product, and storing the fault tree in a storage unit, the fault tree having branches allocated with weighting coefficients; (b) inputting new fault information of the product into the computer; (c) searching the fault tree in accordance with the weighting coefficients based on the fault information stored in the storage unit to thereby determine the cause of the fault; (d) generating and outputting information concerning an adjustment or repair of the product suffering from the fault based on the determined cause of the fault as well as the information concerning the structure and the characteristics of the product; (e) supplying information concerning the timing of the occurrence of the fault, symptoms appearing in the fault, the cause of the fault and the adjustment and repair data to a host computer through a data collecting station to thereby construct a database for the fault information; and (f) the quality of the product based on all or a part of information of the database

Test generation by environment emulation

Abstract: Generation, validation and fault-grading of test patterns, and test and debug of logic circuits, are enhanced by emulation of the logic circuits in programmable gate arrays. Two emulations of the logic circuit are preferably created, one of which is a "good" model containing no faults and the other of which is a "faultable" model into which possible faults may be selectively introduced. A fault is introduced in the faultable model, and the two models are exercised in parallel by applying the same pattern of test vectors to both models. The test vector pattern may be generated by an emulation of the intended operating environment of the logic circuit. Differences in the output signals of the two models indicate that the fault has been detected by the applied test pattern. Application of the test pattern is repeated for each of a sequence of possible faults, to determine the extent to which the test pattern enables detection of faults in the logic circuit. A fault dictionary is produced which includes an indication of the test vector at which each fault is detected, the output signal differences indicative of fault detection, and a log of the faults detected. The faultable emulation is also used for device testing by comparing its outputs to those of a logic circuit, and injecting selected faults (for example, those indicated by comparing failure patterns to fault dictionary entries) to aid in device debug. Techniques are described for modeling faults, sequentially activating the faults in hardware time, preparing a fault dictionary, and extracting a test program in a format adaptable to standard ATE systems, and testing a debugging devices by comparing their behavior to that of a faultable emulation model of the device.

An image forming apparatus provided with self-diagnosis system

Abstract: In an image forming machine, an objective model storage device stores parameter data that represent elements of the machine and relationships among such parameters, and parameter membership functions, and fault diagnosis knowledge A degradation storage device stores a fuzzy qualitative value for a parameter changed by degradation of an element of the machine Preferably, degradation indicative data are converted into fuzzy qualitative values, and the value of the parameter changed by degradation is represented by a fuzzy qualitative value The machine includes sensors for sensing functional states thereof, and providing state data representative of such states The state data sensed by the sensors are converted into fuzzy qualitative values Then, a fault judgement device determines whether or not a fault exists by comparing the obtained fuzzy qualitative values with the parameter data stored in the objective model storage device If the fault judgement device determines that a fault exists, a fault diagnosis device performs fault diagnosis by utilizing, as an initial value, the value of the parameter changed by degradation A specification device specifies fault causes by comparing the result of the diagnosis with the state data which was converted into the fuzzy qualitative values Then, a repair device operates actuators of the machine to overcome the specified fault

Diagnostic Fault Simulation of Sequential Circuits

Abstract: In this work we describe a diagnostic fault simulator for sequential circuits which evaluates the effectiveness of a given test set in distinguishing between faults. Diagnostic fault simulation is performed on several ISCAS89 sequential benchmark circuits using two diferent deterministic test sets for each circuit. Several diagnostic measures are reported, including the diagnostic resolution, the diagnostic power, and the sizes of the indistinguishable fault classes. In addition, lists of indistinguishable faults are generated. Use of the diagnostic fault simulator to diagnose faults, given the output responses of failing devices, is also described.

Principles of fault current limitation by a resonant LC circuit

Abstract: The reduction of fault current is one of the oldest problems of power systems engineering. Fault current reduction permits the interconnection of large networks without replacing circuit breakers, improves transient stability, and reduces the cost of equipment. The paper investigates the reduction of fault current by the insertion of a resonant LC circuit into the transmission line. The device consists of a capacitor and a thyristor-switched inductance, tuned to the supply frequency. The thyristor switches are operated at zero-current-crossing to eliminate the generation of harmonics. The system operation is analysed using analytic methods and transient simulation techniques. A parametric study determines the effect of components and network parameters on the current limiter operation. Design methods and component selection criteria are developed. The results demonstrate that the device can reduce both transient and steady-state fault current significantly. It can be built with commercially available components. The significant operation improvement is expected to justify the cost of the new device.

A new travelling-wave based scheme for fault detection on overhead power distribution feeders

Abstract: The authors present the results of investigations into a new fault location technique for overhead power distribution systems. The scheme is based on detecting fault-induced high-frequency components on distribution lines. This should enable the detection of discharges from the low-level breakdown of insulators, which cannot be detected by conventional methods. The location of a fault is determined by appropriate signal processing of the generated signals on the line. Simulation results are used to illustrate the basic features of the performance of the new scheme on a simple radial 11 kV feeder system. >

A functional fault model for sequential machines

Abstract: A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

A novel approach to delay-fault diagnosis

Abstract: The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

Diagnosis of leakage faults with I DDQ

Abstract: Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.

Fault location techniques for radial and loop transmission systems using digital fault recorded data

Abstract: The authors present digital fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals. The systems under consideration are a 115 kV loop transmission system with data available at two terminals and a 69 kV radial transmission system with data available at one terminal. The data under consideration were recorded using digital fault recorders. The conversion of the data to workable data files and the techniques developed to achieve the highest accuracy in determining the fault location are discussed. Intermediate load buses and loads are considered in determining the fault location. An example of the effect of neglecting the presence of these loads is discussed. The fault location techniques are based on both the apparent impedance concept and the use of the three-phase voltage and current phasors. A test case with the exact fault location is presented. The techniques were developed on an IBM PC. >

An efficient non-enumerative method to estimate path delay fault coverage

Abstract: A method to estimate the coverage of path delay faults of a given test set, without enumerating paths, is proposed. The method is polynomial in the number of lines in the circuit, and thus allows circuits with large numbers of paths to be considered under the path delay fault model. Several levels of approximation, with increasing accuracy and increasing polynomial complexity, are proposed. Experimental results are presented to show the effectiveness and accuracy of the estimate in evaluating the path delay fault coverage. Combining this nonenumerative estimation method with a test generation method for path delay faults would yield a cost effective method to consider path delay faults in large circuits, which are beyond the capabilities of existing test generation and fault simulation procedures, that are based on enumeration of paths.

Delay-fault diagnosis by critical-path tracing

Abstract: A delay fault diagnosis process consisting of simulation of the fault-free circuit with a four-valued logic algebra and critical-path tracing from primary outputs to primary inputs is presented. An alternative to fault simulation, the method requires no delay-size-based fault models and considers only the fault-free circuit. A sensitivity analysis process for improving diagnosis accuracy is also presented. >

Fault diagnosis for the Space Shuttle main engine

Abstract: A conceptual design of a model-based fault detection and diagnosis system is developed for the Space Shuttle main engine. The design approach consists of process modeling, residual generation, and fault detection and diagnosis. The engine is modeled using a discrete time, quasilinear state-space representation. Model parameters are determined by identification. Residuals generated from the model are used by a neural network to detect and diagnose engine component faults. Fault diagnosis is accomplished by training the neural network to recognize the pattern of the respective fault signatures. Preliminary results for a failed valve, generated using a full, nonlinear simulation of the engine, are presented. These results indicate that the developed approach can be used for fault detection and diagnosis. The results also show that the developed model is an accurate and reliable predictor of the highly nonlinear and very complex engine.

Fault indicator with optically-isolated remote readout circuit

Abstract: A fault indicator for indicating at local and remote locations the occurrence of a fault current in a conductor of an AC power distribution system utilizes a liquid crystal display having independent "F" and "N" optical display and shutter elements. Upon occurrence of a fault current a reed switch closes and a portion of the charge on a first capacitor is transferred to a second capacitor, which is connected to the "F" actuator electrodes of the liquid crystal display to cause an "F" to be displayed and an associated optical shutter to open. The "N" actuator electrodes are capacitively coupled to the monitored conductor and system ground to cause an "N" to be displayed and an associated optical shutter to open to indicate that voltage is present on the conductor. First and second light sources are caused to project through respective ones of the optical shutters onto respective first and second photodetectors. A first control circuit responsive to the output of the first photodetector provides a first output signal indicative of the occurrence of a fault. A second control circuit responsive to the second photodectector provides a second output signal indicative of the presence of voltage on the conductor.

Transition fault simulation for sequential circuits

Abstract: ~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

QUIETEST: a methodology for selecting I DDQ test vectors

Abstract: Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current Iddq) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each Iddq measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I DDQ measurement for ail of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.

All Tests for a Fault are Not Eyually Valuable for Defect Detection

Abstract: The standard approach to generating a test set for a logic circuit is to select a set of target fault,s and generate one test for each fault (or at least most of the faults). By far, the most common target fault set is composed of single stuck-at faults. However, many potential manufacturing (non-target) defects are not included in the target fault set, so that their detection is just a fortuitous coincidence. In most cases, many different tests may exist which detect a given single stuck-at fault. However, each of these tests (for the same stuck-at fault) may perform very differently in terms of their non-target defect detection. We investigate this phenomenon empirically using a subset of the ISCXS 85 benchmark circuits, and our results show that extremely wide variations in defective part level are possible over sets of tests which all guarantee 100% single non-redundant stuck-at fault coverage. Our objective in this work is the investigation of non-target defects and their impact on defective part level. Here, our thrust is not to develop new test gene rut i o n methods .

Test pattern generation

Abstract: A method for generating and simulating test patterns to detect faults (57, 63) in an integrated circuit. The method comprises identifying all nets (27) which can potentially be shorted together. Each potential fault (34, 36, 37, 38, 39) is categorized as either a feedback fault or a non-feedback fault. A test pattern is generated to detect the selected potential fault. The test pattern is simulated to determine which additional potential faults are detected by the test pattern. Potential faults which are detected by the test pattern are deleted from the fault list (12). The method is repeated until no potential faults remain on the fault list (12).

WARNING: 100% Fault Coverage May Be Misleading!!

Abstract: In this gaper we show that even when a sequential test generator does a "perfect" job and achieves 100% detectable fault coverage, a circuit passing the test may still exhibit severe testability problems caused by undetectable faults that prevent initialization (FPIs). Thus 100% fault coverage may be a misleading quality indicator, unless undetectable FPIs are accounted for. We present the first algorithm able to identify undetectable FPIs and we report the results obtained for the sequential benchmark circuits. We also discuss the design for testability techniques that make these faults detectable.

Advanced cable fault locator

Abstract: A simple and inexpensive system for real-time location of a fault (40) occurring anywhere in an underground residential distribution (URD) system (schematically represented by circuit model (4)) by analyzing the propagating fault signal at an open point (32) in light of the predetermined propagating velocity of the fault signal.

Detection of undetectable faults using IDDQ testing

Abstract: A new fault model (weak-0 and weak-1 faults) is presented to represent defects in CMOS circuits which may cause degradation of voltage levels without affecting logic values. It is shown that such faults can be effectively detected by IDDQ measurements. A hierarchical methodology is presented for selecting a small number of test vectors for detecting weak faults by IDDQ measurements. The methodology has been implemented in the framework of QUIETEST system. For two VLSI circuits QUIETEST was able to select less than 1% of functional test vectors from the full test set for covering as many weak faults as would be covered if IDDQ was measured upon the application of 100% of the vectors.

Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects

Abstract: Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach relying on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate level test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.

Apparatus for fault detection and isolation

Abstract: An apparatus for fault detection and coupled between a power supply line and a circuit to be powered. When a fault develops in the circuit that causes voltage in the power supply lines to decrease, the power being provided is interrupted from the circuit. Once the fault is removed, power is automatically returned to the circuit.

Fault detection circuit and method for testing a multiple conductor cable having a shield

Abstract: A fault detection circuit for testing conductor-to-conductor and conductor-to-ground faults in multiple conductor shielded cables. The fault detection circuit includes a voltage source that provides a plurality of distinct voltage phases. Each distinct phase from the voltage source is connected through a resistance and a logic circuit to an individual conductor in the cable. The resistance limits the current flowing through the fault detection circuit to reduce the risk of electrical shock to the operator. The logic circuit includes control relays which are responsive to phase-to-phase or phase-to-ground faults in the cable conductors. The logic circuit also provides a visual indication of a fault in the cable.

Multiple fault detection in two-level multi-output circuits

Abstract: It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.

A reconfigurable fault-tolerant system

Abstract: The reconfigurability property of a general form of a majority circuit, which is called two-level error making circuit (2-EMC) is used to build a new dynamic fault-tolerant system. An adaptive voting circuit with provision for online fault detection mechanism is investigated. This new form of a dynamic reconfigurable fault-tolerant system facilitates fault detection and testing procedure of the system. If a fault is detected, the system automatically reconfigures itself so that the faulty unit is isolated and removed from the system and the capability of simultaneous masking of E faulty units is reduced to simultaneous masking of E-1 units. The system can mask up to R-K sequential faults, where R is the degree of redundancy, and K is the grouping parameter of the majority voting circuit, 2-EMC. An alarm signal is provided when critical internal faults in the majority voting circuit are detected. The block design concepts are used to formulate, describe, and construct the general form of the system. >