Showing papers on "Fault indicator published in 1993"

FINE: A fault injection and monitoring environment for tracing the UNIX system behavior under faults

Abstract: The authors present a fault injection and monitoring environment (FINE) as a tool to study fault propagation in the UNIX kernel. FINE injects hardware-induced software errors and software faults into the UNIX kernel and traces the execution flow and key variables of the kernel. FINE consists of a fault injector, a software monitor, a workload generator, a controller, and several analysis utilities. Experiments on SunOS 4.1.2 are conducted by applying FINE to investigate fault propagation and to evaluate the impact of various types of faults. Fault propagation models are built for both hardware and software faults. Transient Markov reward analysis is performed to evaluate the loss of performance due to an injected fault. Experimental results show that memory and software faults usually have a very long latency, while bus and CPU faults tend to crash the system immediately. About half of the detected errors are data faults, which are detected when the system is tries to access an unauthorized memory location. Only about 8% of faults propagate to other UNIX subsystems. Markov reward analysis shows that the performance loss incurred by bus faults and CPU faults is much higher than that incurred by software and memory faults. Among software faults, the impact of pointer faults is higher than that of nonpointer faults. >

Transition fault testing for sequential circuits

Abstract: Addresses the problem of simulating and generating tests for transition faults in nonscan and partial scan synchronous sequential circuits. A transition fault model for sequential circuits is first proposed. In this fault model, a transition fault is characterized by the fault site, the fault type, and the fault size. The fault type is either slow-to-rise or slow-to-fall. The fault size is specified in units of clock cycles. Fault simulation and test generation algorithms for this fault model are presented. The fault simulation algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. Experimental results show that neither a comprehensive functional verification sequence nor a test sequence generated by a sequential circuit test generator for stuck faults produces a high fault coverage for transition faults. Deterministic test generation for transition faults is required to raise the coverage to a reasonable level. With the use of a novel fault injection technique, tests for transition faults can be generated by using a stuck fault test generation algorithm with some modifications. Experimental results for ISCAS-89 benchmark circuits and some AT&T designs are presented. Modifications to test generation and fault simulation algorithms required for partial scan circuits are presented. Experimental results on large benchmark circuits show that a high transition fault coverage can be achieved for the partial scan circuits designed using the cycle breaking technique. >

Fault location based on travelling waves

Abstract: Travelling wave methods of fault location for both underground power cables and overhead power lines have been reported since 1931. Currently few, if any, of the travelling wave overhead line fault location methods which have been reported over the last 60 years are still in service, with only one Type C instrument being available commercially. The authors present results obtained using Type A and D methods from which it is concluded that simple, reliable and accurate fault locators can now be produced using modern micro-electronic technology. The new fault locators can function simultaneously as Type A and D systems. Furthermore the prohibitively high costs of previous implementations have been reduced for both the hardware and, especially, the installation and maintenance.

Fault-based automatic test generator for linear analog circuits

Abstract: Recognizing that specification testing of analog circuits involves a high cost and lacks any quantitative measure of the testing process, we adopt a fault-based technique. With the help of hierarchical fault models for parametric and catastrophic faults, and a very efficient fault simulator, our simulation-assisted technique automatically determines the test frequencies to detect AC faults in linear analog circuits. By a suitable choice of parameters in the test generator, we can either determine the best test (maximize the error between the good and the faulty responses) for every fault (resulting in a large test set), or generate the smallest test set for all the faults. Finally, fault coverage values provide a quantitative evaluation of the final test set.

Delay Fault Coverage and Performance Tradeoffs

Abstract: The main disadvantage of the path delay fault model is that to achieve 100% testability every path must be tested. Since the number of paths is usually exponential in circuit size, all known analysis and synthesis techniques for 100% path delay fault testability are infeasible on most circuits. In this paper, we show that 100% delay fault testability is not necessary to guarantee the speed of a combinational circuit. There exist path delay faults which can never impact the circuit delay (computed using any correct timing analysis method) unless some other path delay faults also affect it; hence these delay faults need not be considered in delay fault testing. Next, assuming only the existence of robust delay fault tests for a very small set of paths, we show how the circuit speed can be selected such that 100% robust delay fault coverage is achieved.

Robustness issues in fault-tolerant control

Abstract: Provides a perspective on the state of the art in robust approaches to fault-tolerant control and gives some indication of ways in which the research may best proceed. Key themes are the individual robustness properties of fault detection, fault isolation and controllers used as elements in a fault-tolerant system. Comparisons between active and passive approaches are made and emphasis is placed on the overall robustness properties of the fault-tolerant control system.< >

Automatic fault location system

Abstract: A fault location system comprises voltage/current transducers 10A, 10B located at terminals A and B, respectively; digital relays 12A and 12B respectively coupled to transducer blocks 10A and 10B; and a fault location estimation processor 14, which may comprise a substation controller at substation S A or substation S B , a relay at A or B, a stand alone computer at A or B, or a computer at a central location. The digital relays receive analog voltage and current signals (V A , I A , V B , I B ) from the respective transducers and output digital phasor or oscillographic data to the fault location estimation block. The fault location estimation block is programmed to provide the fault location parameter m. The fault location estimation provided by the inventive technique is unaffected by the fault resistance, load current, mutual coupling effects from a parallel line, uncertainties in zero sequence values, shunt elements, and X/R characteristic of the system. The fault location can be estimated accurately even in cases of substantial resistance and load flow. In addition, the invention does not require synchronization of the data received from the respective A and B terminals, nor does it require pre-fault data or fault type selection.

CMOS bridges and resistive transistor faults: IDDQ versus delay effects

Abstract: Beyond the static stuck-at fault model, delay fault testing and static overcurrent testing have been suggested as approaches yielding reasonable fault coverage in CMOS circuits. Based on detailed simulations of resistive stuck-on-, stuck-open-, and bridging faults for typical CMOS circuits, this paper presents an analysis of their detectability and requirements for current and timing resolutions in overcurrent and delay fault testing. >

Sub-cycle digital distance relay

Abstract: A sub-cycle digital distance relay which uses only the first N/2 samples after a fault to calculate the distance to the fault using a Full Cycle Fourier Algorithm which operates on N samples, where N is the number of samples taken in a cycle of the power signal. The DC offset in the first N/2 samples taken after detection of the fault is cancelled using the N/2+1 sample taken after detection of the fault. The resulting DC adjusted N/2 samples are then multiplied by -1 in order to take advantage of the symmetry of the sine wave of the power signal in estimating the remaining N/2 samples of the first cycle of the power signal after detection of the fault. By so calculating N/2 artificial samples from the first N/2 actual samples taken after the fault, the digital distance relay of the invention can estimate the distance to the fault and thus provide a reliable trip signal in less than one cycle of the power signal. The technique of the invention is used to implement a high-speed tripping mode for use in conjunction with conventional tripping schemes to provide a more reliable tripping signal in a minimum amount of time after the detection of the fault, thereby providing improved fault protection for the power transmission components.

Fault injection using boundary scan

Abstract: A system and method for fault injection utilizing boundary scan includes the provision of an additional fault injection register to the standard JTAG architecture in order to allow the intentional introduction of faults into a device or module forming part of a system under test. Through the use of the fault injection register of the present invention, faults may be intentionally introduced and the system response to such faults monitored and analyzed independently of the system software and without the use of mechanical probes or the like for introducing the fault. The system and method of the present invention is readily integrated with the existing test functions of the standard IEEE 1149.1 boundary scan architecture.

Model based alarm coordination

Abstract: A model-based alarm coordination system coordinates primary and secondary alarm notifications in order to ascertain whether they are caused by a single fault, or multiple faults, in a complex electrical system. The alarm coordination function is part of a larger overall Fault Management Support (FMS) system. The FMS system is a framework that, when combined with object-specific fault management parts, offers uniform fault management functions to managed objects (MOs) within the electrical system. Each MO is viewed as a self-contained, functional unit, and is responsible for its own internal fault management. Therefore, there are no global or centralized fault management functions. Object relation models, based on functional dependencies between objects, are used to automatically solve the alarm coordination problem which arises when a large number of faults are reported in response to a single fault which causes out-of-specification performance in many dependent objects. Little object-specific programming is required.

Detection of faults of filter capacitors in a converter. Application to predictive maintenance

Abstract: One of the most frequent reasons of breakdown of static power converters, and in particular switch mode power supplies, is the failure of filter electrolytic capacitors. With the use of time-worn capacitors, or by modelling the faults artificially, the authors have developed a fault indicator. By comparing the latter with data representing the system during normal running, they have achieved an estimate of imminent failure. >

Recognizing animal-caused faults in power distribution systems using artificial neural networks

Abstract: Artificial neural networks are used to recognize the causes of faults in power distribution systems, based on fault currents information collected for each outage. Actual field data are used. The methodology and implementation of neural networks and fuzzy logic for the identification of animal-caused distribution faults are presented. Satisfactory results are obtained, and the developed methodology can be easily generalized and used to identify other causes of faults in power distribution systems. >

A model-based approach to fault localisation in power transmission networks

Abstract: The basic idea of model-based diagnosis is to exploit knowledge about the structure and behaviour of the physical system to be diagnosed in order to identify diagnoses from discrepancies between observed and predicted behaviour. In this paper, we describe the application of model-based diagnosis to the problem of fault localisation in power transmission networks. We also show that the resulting system, DPNet, has an extended competence w.r.t. rule-based approaches (treatment of unknown and multiple faults) while requiring less development effort because of the use of component libraries in the model-based approach.

A fast and accurate gate-level transient fault simulation environment

Abstract: Mixed analog and digital mode simulators have been available for accurate transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. The authors describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. The simulation environment uses a timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses high level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The simulation environment is demonstrated on ISCAS-89 sequential benchmark circuits.

Real-Time Fault Detection on Textiles Using Opto-electronic Processing:

Abstract: This work is concerned with the study of an automatic fault detection system for textiles. Opto-electronic data processing makes it possible to detect and characterize faults. The method is based o...

Distributed on-line diagnosis in the presence of arbitrary faults

Abstract: This paper introduces a new fault model for system-level diagnosis and a class of online distributed diagnosis algorithms that operate correctly in the presence of fault nodes that disseminate arbitrarily corrupted diagnostic information. The fault model addresses the practical issue of designing an internode test to cover diagnosis algorithm operation. Since an explicit test to detect arbitrary failures is not practical, evidence of a node's faulty behavior is provided by examining diagnositic messages exchanged by the node. In many practical systems, algorithm overhead using the new fault model is only twice that required for algorithms using the PMC fault model. The key results include a description of the new fault model, the specification of a class of online distributed diagnosis algorithms that use this fault model, and proofs of their correctness.

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

Abstract: In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.

Method of finding faults in a branched electrical distribution circuit

Abstract: A PN modulated signal is applied to an end of a network electrical distribution circuit The signal produces a snapshot trace of energy reflected from various discontinuities along the circuit, including a fault Because the fault absorbs a large part of the energy in the applied signal, reflections from discontinuities in the same branch as the fault but farther from the input are reduced in amplitude By knowing the position of the branches and various discontinuities, such as transformers, the position of the fault can be logically determined If the fault is a high resistance fault a high voltage pulse is applied to the end of the circuit The PN signal is initially sensed at a time when the fault has a low resistance because of arcing due to the high voltage pulse

Faulty behavior of storage elements and its effects on sequential circuits

Abstract: It is often assumed that the faults in storage elements (SEs) can be modeled as output/input stuck-at faults of the element. They are implicitly considered equivalent to the stuck-at faults in the combinational logic surrounding the SE cells. Transistor-level faults in common SEs are examined here. A more accurate higher level fault model for elementary SEs that better represents the physical failures is presented. It is shown that a minimal (stuck-at) model may be adequate if only modest fault coverage is desired. The enhanced model includes some common fault behaviors of SEs that are not covered by the minimal fault model. These include data-feedthrough and clock-feedthrough behaviors, as well as problems with logic level retention. Fault models for complex SE cells can be obtained without a significant loss of information about the structure of the circuit. The detectability of feedthrough faults is considered. >

Method and a device for determining a fault on a transmission line

Abstract: A method and a device for determining the distance from a measuring station to a fault on a transmission line based on a fault model of a transmission network while taking into consideration the zero-sequence impedance and, where assuming a fault current, while taking into consideration the feeding of fault current to the fault point from both ends of the transmission line (FIG. 3 ).

New methods of improving parallel fault simulation in synchronous sequential circuits

Abstract: A highly successful parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. We propose several new techniques which further reduce the fault simulation time of HOPE. The new techniques are: functional fault injection, static fault ordering by fanout free regions and dynamic fault ordering of potentially detected faults. The three methods are incorporated into HOPE and called HOPE1.1. HOPE1.1 shows significant improvement in performance for all the benchmark circuits experimented as compared to HOPE. Experimental results show that HOPE1.1 is especially effective for large circuits. For s35932 which is the largest circuit experimented with, the number of events is reduced by 24%, and the CPU time by 53% compared to HOPE.

Testing interconnects: a pin adjacency approach

Abstract: This paper looks at a new fault model used for shorts between nets on a PCB, the pin-adjacency fault model, and the implementation of two algorithms. The pin-adjacency detection and diagnosis algorithms for detecting and diagnosing these bridging faults. The authors represent the nets and their likelihood to short as a graph, and in conjunction with the new algorithms are able to generate reduced test sets. This represents a huge saving over existing algorithms which assume that any two nets are likely to short, as opposed to the new more realistic pin-adjacency fault model. >

Development of expert system for operation at substation

Abstract: An expert system that offers support information in substation fault occurrence is described, focusing on a method for fault section estimation. This system edits fault information and estimates the fault section. With respect to the fault section. With respect to fault section estimation, a method that makes maximum use of sequential information on protective relay and circuit breaker operation even for complicated fault conditions involving multiple faults and incorrect operation or incorrect nonoperation of protective relays and circuit breakers. This system is undergoing field test in a commercial EHV substation, and so far normal operation is reported. >

Fault behavior dictionary for simulation of device-level transients

Abstract: The paper presents a methodology for the simulation of massive number of device-level transient faults. Fault injection locations and the gate around those locations are extracted and evaluated with SPICE. The extracted sub-circuits are exercised exhaustively while fault-injections are performed. Faulty behavior at the outputs of each sub-circuit is recorded in a dictionary, along with the associated input vector, fault-injection time, and location. The recorded logical errors are injected concurrent transient simulator is developed to allow simultaneous evaluation of a massive number of fault-injections, in a single simulation pass. The methodology is illustrated by a case study of MC68000 microprocessor.

Simulation of non-classical faults on the gate level - The fault simulator COMSIM

Abstract: COMSIM is a fault simulator for combinational circuits which can efficiently handle various gate level fault models Stuck-at faults, function conversions, bridging faults, transition faults as well as multiple faults of all types and faults with additional fault detection conditions, can be simulated in one pass This offers a practical approach to solve the conflict between the accuracy of fault modeling, which usually requires a low level circuit description, and the desired performance of the simulation tools, which forbids the use of a low level description In a preprocessing step which has to be performed only once for a given cell library, the effects of realistic faults are investigated for each gate type These fault effects are mapped onto gate level faults and stored in a fault library The specification of a corresponding gate level fault is almost always possible due to the wide variety of gate level fault models which can be simulated by COMSIM Simulation results are given which demonstrate the practicability and the advantages of library-based fault modeling The experimental results show that COMSIM can efficiently handle non-classical faults on the gate level >

A novel approach for distribution fault analysis

Abstract: This paper proposes to use four different measures: actual values, normalized values, relative values, and likelihood values for power systems' distribution faults analysis. This paper also discusses the general and local properties of distribution faults. The likelihood measure, based on the local region properties, provides important information for distribution fault cause identification when the fault cause is not known. Tree faults on the Duke Power System are used in this paper for illustration purposes. The proposed measures' analysis and discussion can be easily generalized for different types of distribution faults in other utility companies. >

Analogue fault identification based on power supply current spectrum

Abstract: A fault dictionary approach using power supply current spectrum measurements for fault location in analogue active circuits is presented. A discrimination factor is introduced for efficient fault identification. Representative results using an active filter example are given, showing the effectiveness of the proposed technique.

Fault simulation of parametric bridging faults in CMOS IC's

Abstract: The authors point out that the simulation of resistive bridging faults inside complex CMOS macrogates requires proper evaluation of resistances, in order to correctly determine realistic fault coverages. Here, an approach applicable to a large category of faults (bridgings, transistor stuck-ons, and node stuck-ats) that give rise to resistive paths between power supply and ground, and hence are all covered by the general term 'bridging faults,' is presented. This method, which avoids the single-fault-injection procedure, fault analysis is performed inside the macrogates aimed to determine the threshold resistance, thus discriminating whether or not a given fault is detectable as a logic error. This analysis is performed inside CMOS macro-gates whose output is observable. To fully characterize the quality of a test sequence with regard to resistive bridging faults, a new definition of fault coverage is presented, because the common concept of fault detection is not applicable to parametric faults. >

Fault isolation in an integrated diagnostic environment

Abstract: The use of information flow models to conduct efficient fault isolation strategies is described. Of particular concern is optimizing diagnosis to minimize some objective cost function. A technique that can include multiple cost criteria such as test time, skill level, and failure frequency, as well as information value, is discussed. >