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Showing papers on "Fault indicator published in 2005"


Journal ArticleDOI
TL;DR: In this article, an artificial neural network (ANN) and support vector machine (SVM) approach for locating faults in radial distribution systems is presented, which uses measurements available at the substation, circuit breaker and relay statuses.
Abstract: This paper presents an artificial neural network (ANN) and support vector machine (SVM) approach for locating faults in radial distribution systems. Different from the traditional Fault Section Estimation methods, the proposed approach uses measurements available at the substation, circuit breaker and relay statuses. The data is analyzed using the principal component analysis (PCA) technique and the faults are classified according to the reactances of their path using a combination of support vector classifiers (SVCs) and feedforward neural networks (FFNNs). A practical 52 bus distribution system with loads is considered for studies, and the results presented show that the proposed approach of fault location gives accurate results in terms of the estimated fault location. Practical situations in distribution systems, such as protective devices placed only at the substation, all types of faults, and a wide range of varying short circuit levels, are considered for studies. The results demonstrate the feasibility of applying the proposed method in practical distribution system fault diagnosis.

349 citations


Journal ArticleDOI
TL;DR: In this paper, the authors proposed a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis, which gives rms profiles of the fault currents of interest (IIDG contributions and the fault current the protective device will see).
Abstract: This paper shows that the current an inverter interfaced distributed generator (IIDG) contributes to a fault varies considerably, due mainly to fast response of its controller. This paper proposes a method to extend the conventional fault analysis methods so that IIDG contribution can be estimated in the fault analysis. The proposed method gives rms profiles of the fault currents of interest (IIDG contribution and the fault currents the protective device will see). Test results, based on a prototype feeder, show that the proposed approach can estimate the fault current's contributions under both balanced and unbalanced fault conditions.

240 citations


Journal ArticleDOI
TL;DR: In this paper, a fuzzy-logic-based algorithm to identify the type of faults for digital distance protection system has been developed, which is able to accurately identify the phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault resistances, inception angle, and loading levels.
Abstract: In this paper, a fuzzy-logic-based algorithm to identify the type of faults for digital distance protection system has been developed. The proposed technique is able to accurately identify the phase(s) involved in all ten types of shunt faults that may occur in a transmission line under different fault resistances, inception angle, and loading levels. The proposed method needs only three line-current measurements available at the relay location and can perform the fault classification task in about a half-cycle period. Thus, the proposed technique is well suited for implementation in a digital distance protection scheme.

221 citations


Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this article, a performance evaluation for the inverter connected to the machine with variable stator voltage and frequency is presented, showing the influence of the applied standard field oriented control on the currents during a fault.
Abstract: Variable speed drives have become industrial standard in many applications Therefore fault diagnosis of voltage source inverters is becoming more and more important One possible fault within the inverter is an open circuit transistor fault An overview of the different strategies to detect this fault is given, including the algorithms used to localize the open transistor Previous work showed significant differences among the available methods to detect such a fault for a mains side active rectifier This paper extends the performance evaluation for the inverter connected to the machine with variable stator voltage and frequency Simulation results are presented They show the influence of the applied standard field oriented control on the currents during a fault An experimental setup in the laboratory is used to validate simulation results Typical detection results are presented including time-to-detection measurements Robust detection of open transistor faults has been found to be possible

179 citations


Journal ArticleDOI
TL;DR: In this paper, a synthetic spectral analysis is proposed to deal with wideband frequency responses of each phase, which augments low and medium-frequency components, and equalizes the frequency intervals of a resulting combined curve by a log-frequency interpolation.
Abstract: A transformer is one of the most important units in power networks; thus, fault diagnosis of transformers is quite significant. In this paper, the frequency-response analysis, deemed as a suitable diagnostic method for electrical and/or mechanical faults of a transformer, is employed to make a decision over a defective phase. To deal with wideband frequency responses of each phase, a synthetic spectral analysis is proposed, which augments low- and medium-frequency components, and equalizes the frequency intervals of a resulting combined curve by a log-frequency interpolation. Furthermore, for discriminating a defective phase through computing overall amounts of deviation with other phases, the two well-known criteria and three proposed criteria are examined with experiment data. The overall diagnosis results show that the proposed criterion discriminates a defective phase with the highest average hit ratio among all of the provided criteria for selected faults.

150 citations


Journal ArticleDOI
TL;DR: Based on the class of nonlinear systems and sensor bias faults under consideration, the stability and learning properties of the fault isolation estimators are obtained, adaptive thresholds are derived for the isolation estimator, and fault isolability conditions are rigorously investigated, characterizing the classof nonlinear faults that are isolable by the proposed scheme.
Abstract: This note presents a robust fault isolation scheme for a class of nonlinear systems with sensor bias type of faults. The proposed fault diagnosis architecture consists of a fault detection estimator and a bank of isolation estimators, each corresponding to a particular output sensor. Based on the class of nonlinear systems and sensor bias faults under consideration, the stability and learning properties of the fault isolation estimators are obtained, adaptive thresholds are derived for the isolation estimators, and fault isolability conditions are rigorously investigated, characterizing the class of nonlinear faults that are isolable by the proposed scheme. A simulation example is used to illustrate the effectiveness of the sensor bias fault isolation methodology.

145 citations


Proceedings ArticleDOI
05 Apr 2005
TL;DR: In this paper, the authors describe one-and two-ended impedance-based fault location experiences using simple reactance, Takagi, zero-sequence current with angle correction, and twoended negative-sequence.
Abstract: In this paper, we describe one- and two-ended impedance-based fault location experiences. We define terms associated with fault location and describe several impedance-based methods of fault location (simple reactance, Takagi, zero-sequence current with angle correction, and two-ended negative-sequence). We examine several system faults and analyze the performance of the fault locators given possible sources of error (short fault window, nonhomogeneous system, incorrect fault type selection, etc.). Finally, we show the laboratory testing results of a two-ended method, where we automatically extracted a two-ended fault location estimate from a single end.

132 citations


Patent
26 Sep 2005
TL;DR: In this article, a fault module supports detection, analysis, and/or logging of various faults in a processor system, and it is provided on a multi-core, single die device.
Abstract: A fault module supports detection, analysis, and/or logging of various faults in a processor system. In one embodiment, the system is provided on a multi-core, single die device.

122 citations


Journal ArticleDOI
24 Oct 2005
TL;DR: In this paper, the authors present a systematic classification of all electrical faults, short and open-circuits, in the switched reluctance drive (excluding the controller itself), and the investigation of fault patterns and possible remediation.
Abstract: The switched reluctance drive is known to be fault tolerant, but it is not fault free. The goals of this study are the systematic classification of all electrical faults, short-and open-circuits, in the switched reluctance drive (excluding the controller itself), and the investigation of fault patterns and possible remediation. Each situation is analyzed via finite element analysis, and/or experiments. The transient effects during the faults are described. Possible remediation schemes other than disabling the faulted phase are explored. There is a particular focus on switch short-circuit for which new results are presented.

120 citations


Journal ArticleDOI
TL;DR: In this paper, the authors present the development, simulation results, and field tests of an automated fault location system for primary distribution networks, which is able to identify the most probable fault locations in a fast and accurate way.
Abstract: This paper presents the development, simulation results, and field tests of an automated fault location system for primary distribution networks. This fault location system is able to identify the most probable fault locations in a fast and accurate way. It is based on measurements provided by intelligent electronic devices (IEDs) with built-in oscillography function, installed only at the substation level, and on a database that stores information about the network topology and its electrical parameters. Simulations evaluate the accuracy of the proposed system and the experimental results come from a prototype installation.

111 citations


Journal ArticleDOI
TL;DR: In this paper, a fault location algorithm for parallel transmission lines using two terminal currents is proposed, which is based on the fact that the difference between voltage distributions, calculated from two terminals currents, is the smallest at fault point.
Abstract: This paper presents a novel time-domain fault location algorithm for parallel transmission lines using two terminal currents. Parallel transmission lines with faults can be decoupled into the common component net and differential component net. Since the differential component net is only composed of the parallel lines and its terminal voltages equal zero, the proposed algorithm is based on the fact that the difference between voltage distributions, calculated from two terminal currents, is the smallest at fault point. To be practical, unsynchronized data and the transient transferring ability of the current transformer are taken into consideration. The algorithm needs a very short data window, and any segment of current data can be used to locate faults. The proposed algorithm is verified successfully using the simulation data generated by the frequency-dependent line model of the Alternative Transients Program and the field recording data provided by traveling-wave fault locators. Locating results show the satisfactory accuracy of the algorithm for various fault types, fault distances, and fault resistances.

01 Jan 2005
TL;DR: A practical implementation of a fault attack implemented on a Silvercard (a freely available smart card based on a PIC16F877 produced by Microchip) to effectively reduce the number of rounds of a secret key algorithm.
Abstract: This paper presents a practical implementation of a fault attack implemented on a Silvercard (a freely available smart card based on a PIC16F877 produced by Microchip). The aim of the fault attack is to effectively reduce the number of rounds of a secret key algorithm. The simplest case of reducing the number of rounds to one was chosen to facilitate subsequent cryptanalysis. The fault injection method used is a glitch on the power supplied to the smart card. The manner in which this changes the functioning of the smart card is described, followed by how this effect can then be used to produce the desired result. A description of how this was applied to an AES implementation is given. Lastly, Various generic countermeasures are discussed to show how this type of attack can be prevented.

Journal ArticleDOI
TL;DR: In this article, a finite element model was used to perform simulations under three types of fault conditions, single-phase open circuit fault, phase-to-phase terminal short-circuit, and internal turn-toturn shortcircuit have been studied.
Abstract: Three-phase trapezoidal back-EMF permanent magnet (PM) machines are used in many applications where the reliability and fault tolerance are important requirements. Knowledge of the machine transient processes under various fault conditions is the key issue in evaluating the impact of machine fault on the entire electromechanical system. The machine electrical and mechanical quantities whose transient behaviors are of importance under fault conditions include the voltages and currents of the coils and phases, the electromagnetic torque, and the rotor speed. Experimental test based on true machines for such a purpose is impractical for its high cost and difficulty to make. Computer simulation based on the finite element method has shown its effectiveness in fault study in this paper. Before the finite element model was used to perform simulations under fault conditions, it was validated by test data under normal conditions. Three types of fault conditions-single-phase open circuit fault, phase-to-phase terminal short-circuit, and internal turn-to-turn short-circuit have been studied.

Patent
27 Oct 2005
TL;DR: In this paper, a method for fault estimation based on residuals (302) of detected signals (301) includes determining an operating regime based on a plurality of parameters, extracting (202) predetermined noise standard deviations of the residuals corresponding to said operating regime and scaling the residual residuals; calculating (203) a magnitude of a measurement vector of the scaled residuals and comparing the magnitude to a decision threshold value; extracting (204) a mean direction and a fault level mapping for each of a pluralityof fault types, based on the operating regime, calculating (205) a
Abstract: A method for performing a fault estimation based on residuals (302) of detected signals (301) includes: determining (201) an operating regime based on a plurality of parameters; extracting (202) predetermined noise standard deviations of the residuals corresponding to said operating regime and scaling the residuals; calculating (203) a magnitude of a measurement vector of the scaled residuals and comparing the magnitude to a decision threshold value; extracting (204) a mean direction and a fault level mapping for each of a plurality of fault types, based on the operating regime; calculating (205) a projection of the measurement vector onto the mean direction of each of the plurality of fault types; determining (206) a fault type based on which projection is maximum; and mapping (207) the projection to a continuous-valued fault level using a lookup table.

Journal ArticleDOI
TL;DR: In this paper, a general architecture for fault tolerant control is proposed based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBJ parameterization to quantify the performance of the fault tolerant system.
Abstract: A general architecture for fault tolerant control is proposed. The architecture is based on the (primary) YJBK parameterization of all stabilizing compensators and uses the dual YJBK parameterization to quantify the performance of the fault tolerant system. The approach suggested can be applied for additive faults, parametric faults and for system structural changes. The modelling for each of these fault classes is described. The method allows for design of passive as well as for active fault handling. Also, the related design method can be fitted either to guarantee stability or to achieve graceful degradation in the sense of guaranteed degraded performance. A number of fault diagnosis problems, fault tolerant control problems, and feedback control with fault rejection problems are formulated/considered, mainly from a fault modelling point of view. The method is illustrated on a servo example including an additive fault and a parametric fault.

Journal ArticleDOI
TL;DR: In this paper, an artificial neural network (ANN)-based scheme for fault diagnosis of power transformers is presented, which is designed to detect the fault, estimate the faulted side, classify the fault type and identify the phase.

Proceedings ArticleDOI
01 Jan 2005
TL;DR: In this paper, a fast fault detection method for microgrid system based on micro-sources equipped with power electronics interfaces is explored, which provides reliable and fast detection for different types of faults within the micro-grid.
Abstract: In this paper a fast fault detection method for Microgrid system based on micro-sources equipped with power electronics interfaces is explored. This method provides reliable and fast detection for different types of faults within the micro-grid. The micro-source output voltages are monitored and then converted to dc quantities in the d-q reference frame. Thus, any disturbance at the micro-source output due to any type of fault is reflected as disturbances in the d-q values. The disturbance is used to detect the fault and this leads to the initiation of the associated breaker to isolate the faulted section from the network. Analysis and simulation results are presented for different types of faults within the micro-grid

Journal ArticleDOI
TL;DR: In this paper, the authors describe the design and implementation of a fault tolerant magnetic bearing system for a turbo-molecular vacuum pump, which can cope with actuator/amplifier faults, as well as faults in position sensors.
Abstract: One of the obstacles for a magnetic bearing for use in a wide range of industrial applications is the failure modes associated with magnetic bearings, which are not expected for conventional passive bearings. These failure modes include electric power outage, power amplifier faults, position sensor faults, and the malfunction of controllers. Fault tolerant magnetic bearing systems have been proposed so that the system can operate in spite of some faults in the system. In this paper, we describe the design and implementation of a fault tolerant magnetic bearing system for a turbo-molecular vacuum pump. The system can cope with actuator/amplifier faults, as well as faults in position sensors, which are the two major fault modes in a magnetic bearing system.

Journal ArticleDOI
TL;DR: In this paper, a nonlinear observer-based principle combined with Wald's sequential test is proposed for detecting faults in electro-hydraulic servo-positioning systems using a non-linear observer.

Proceedings Article
01 Jan 2005
TL;DR: This paper summarizes the existing research on DFA, describes and analyzes a differential attack on various algorithms like DES, RSA, IDEA, RC5, DSA and other vulnerable ciphers, and discusses some of the ways to prevent the Differential Fault Analysis.
Abstract: Commercial ventures and financial institutions have proposed and are relying upon smartcards and other security processors as a method for storing and transacting electronic currency. As users begin to accept electronic wallets as a viable option for storing their assets, the security community has placed these devices under closer scrutiny. The idea of using computational faults to break tamper resistant cryptographic devices has been recently highlighted in lot of researches. Biham and Shamir named this form of attack as Differential Fault Analysis (DFA). This paper summarizes the existing research on DFA, describes and analyzes a differential attack on various algorithms like DES, RSA, IDEA, RC5, DSA and other vulnerable ciphers. This paper also discusses some of the ways to prevent the Differential Fault Analysis. 0. Introduction Side-channel attacks occur when an attacker is able to use some additional information leaked from the implementation of a cryptographic function to cryptanalyze the function. Given enough sidechannel information, it is trivial to break a cipher. An attacker who can, for example, learn every input into every S-box in every one of DES's rounds can trivially calculate the key. Differential Fault analysis (DFA) fall under side channel attacks. The purpose of this paper is to outline the Differential Fault Analysis (DFA) method of attacking cryptographic algorithms. This paper is intended to provide a survey of DFA in terms of the how the attack is accomplished and which algorithms are vulnerable to this form of attack. The document is divided into four parts the first part provides an introduction to fault analysis. The second deals with differential fault analysis technique. The third part outlines the attacks on various algorithms. The fourth part looks at the ways that this attack can be avoided. 1. Overview of Fault Analysis Fault Analysis relates to the ability to investigate ciphers and extract keys by generating faults in a system that is in the possession of the attacker, or by natural faults that occur. Faults are most often caused by changing the voltage, tampering with the clock, or by applying radiation of various types. The attacks are based on encrypting the same piece of data (which are not necessarily known to the attacker) twice and comparing the results. A one-bit difference indicates a fault in one of the operations. Now a short computation can be applied for DES for example to identify the round in which the error has occurred. A whole set of operations can be carried out recover the DES sub-key which is the sub-key of the last round the. When this sub-key is known the attacker can either guess the missing 8 bits or simply peel of the last round for which he knows the sub-key and perform the attack on a reduced DES. Another type of fault analysis is the nonDifferential Fault analysis, but this is based on causing permanent damage to devices for the purpose of extracting symmetric keys. It must be mentioned that a trait of such attacks is that they do not require correct cipher texts. This leads to the attacker being able to make use of natural faulty units, without himself tampering with them. [1] Types of Faults Transient faults Consider a certification authority (CA) that is constantly generating certificates and sending them out to clients. Due to random transient hardware faults the CA might generate faulty certificates on rare occasions. If a faulty certificate is ever sent to a client, that client will be able to break the CA’s system and generate fake certificates. Note that on various systems, a client is alerted when a faulty certificate is received. Latent faults Latent faults are hardware or software bugs that are difficult to catch. As an example, consider the Intel floating point division bug. Such bugs may also cause a CA to generate faulty certificates from time to time. Induced faults When an adversary has physical access to a device she may try to purposely induce hardware faults. For instance, one may attempt to attack a tamper-resistant device by deliberately causing it to malfunction. The erroneous values computed by the device enable the adversary to extract the secret stored on it. [2] 2. Differential fault Analysis (DFA) In 1996, a new attack on cryptographic devices was proposed by researchers at Bellcore. This attack depends on introducing errors into key-dependent cryptographic operations through physical intrusion. Soon after, the initial Bellcore work which focused on public-key techniques was extended and applied to secret-key encryption techniques. It also motivated a series of discussions on the capabilities of secure hardware as a means of keeping the details of certain cryptographic algorithms confidential, and a variety of different threat models have now been considered as a result of their work. The reliance of many security systems on the use of secure hardware or secure processing makes a full evaluation of the potential of fault analysis very important. For developers and users alike an increased awareness of the threat posed by new and novel methods of cryptanalysis allows the development of more secure cryptographic implementations. In this note we will summarize these recent results and in particular we will assess their practical significance when applied to RSA and DES. [3] 3. Differential Fault Analysis on Various Algorithms In the next subsection we will discuss Differential Fault Attack (DFA) on DES. 3.1. DFA on DES The attack follows the Bellcore fundamental assumption that by exposing a sealed tamperproof device such as a smart card to certain physical effects (e.g., ionizing or microwave radiation), one can induce with reasonable probability a fault at a random bit location in one of the registers at some random intermediate stage in the cryptographic computation. Both the bit location and the round number are unknown to the attacker. It is further assumed that the attacker is in physical possession of the tamperproof-device, so that he can repeat the experiment with the same cleartext and key but without applying the external physical effects. As a result, he obtains two ciphertexts derived from the same (unknown) cleartext and key, where one of the ciphertexts is correct and the other is the result of a computation corrupted by a single bit error during the computation. For the sake of simplicity, we assume that one bit of the right half of the data in one of the 16 rounds of DES is flipped from 0 to 1 or vice versa, and that both the bit position and the round number are uniformly distributed. In the first step of the attack the round in which the fault occurred is identified. If the fault occurred in the right half of round 16, then only one bit in the right half of the ciphertext differs between the two ciphertexts. The left half of the ciphertext can differ only in output bits of the S box (or two S boxes) to which this single bit enters, and the difference must be related to non-zero entries in the difference distribution tables of these S boxes. In such a case, the six key bit of each such S box in the last round can be guessed, and any value which disagrees with the expected differences of these S boxes discarded (e.g., differential cryptanalysis). If the faults occur in round 15, we can gain information on the key bits entering more than two S boxes in the last round: the difference of the right half of the ciphertext equals the output difference of the F function of round 15. We guess the single bit fault in round 15, and verify whether it can cause the expected output difference, and also verify whether the difference of the right half of the ciphertext can cause the expected difference in the output of the F function in the last round (e.g., the difference of the left half of the ciphertext XOR the fault). If successful, we can discard possible key values in the last round, according to the expected differences. We can also analyze the faults in the 14 round in a similar way. We use counting methods in order to find the key. In this case, we count for each S box separately, and increase the counter by one for any pair which suggests the sixbit key value by at least one of its possible faults in either the 14, 15, or 16 round. This attack finds the last sub-key. Once this sub-key is known, we can proceed in two ways: We can use the fact that this sub-key contains 48 out of the 56 key bits in order to guess the missing 8 bits in all the possible 2=256 ways. Alternatively, we can use our knowledge of the last sub-key to peel up the last round (and remove faults that we already identified), and analyze the preceding rounds with the same data using the same attack. This latter approach makes it possible to attack triple DES (with 168 bit keys), or DES with independent subkeys (with 768 bit keys). [5] 3.2. Differential Fault Analysis on RSA Direct attacks on the famous RSA cryptosystem seem to require that one has to factor the modulus. The attack on RSA algorithm is as follows: Let n be the product of two primes p and q in RSA, e the public exponent which is publicly known and d be the private exponent stored inside the tamperproof device. Let M be a plaintext, then the corresponding ciphertext is C = M mod n. Denote the binary representation of the private exponent as d = d (t-1) |d (t-2)| ...|d (i)|...|d (1) |d (0), Where: d (i), takes value 1 or 0, is the i bit, t is the number of bits of d x|y denotes concatenation of x and y. Further, we denote C (0) = C, C(1) = C mod n, C(2) = C mod n, ..., C(t-1) = C. Given C and d, the corresponding plaintext M can be expressed as M =(C(t-1))(C(t-2) )...(C(i)) ...(C(1))(C(0))mod n. Attack 1: Suppose that one bit in the binary representation of d is changed from 1 to 0 or vice versa, and that the faulty bit position is randomly located. An attacker arbitrarily chooses a plaintext M and computes the ciphertext C. He then applies external physical effects to the tampe

Journal ArticleDOI
TL;DR: An advanced fault detection and isolation technique was developed for the steam generator system of a typical pressurized water reactor (PWR) plant and the implementation of the FDI algorithm for both instrument and actuator monitoring is demonstrated.

Proceedings ArticleDOI
12 Jun 2005
TL;DR: Based on the sudden reduction of absolute value of the change rate of power swing centre voltage (PSCV), the presented detector can detect the symmetrical fault reliably and sensitively in two cycles.
Abstract: Distance relay should be blocked during power swing to ensure the reliability, but still should trip as soon as possible after an internal fault occurs during power swing. It was very difficult to detect the symmetrical fault reliably and fast during power swing with complex power swing conditions and fault conditions considered. This paper presents a new fast detector of symmetrical fault during power swing. Based on the sudden reduction of absolute value of the change rate of power swing centre voltage (PSCV), the presented detector can detect the symmetrical fault reliably and sensitively in two cycles. This detector is easy to set and immune to the swing period, fault arc, fault location and power angle. EMTP simulations and real-time digital simulator system (RTDS) tests prove the presented detector is fast, sensible and reliable.

Journal ArticleDOI
TL;DR: In this paper, transient pattern analysis is explored as a tool for fault detection and diagnosis of an HVAC system, and the results show that the evolution of fault residuals forms clear and distinct patterns that can be used to isolate faults.

Patent
24 Jun 2005
TL;DR: In this paper, a system and method for fault detection in turbine engines and other mechanical systems that have nonlinear relationships is presented. But the authors focus on the ability of the system to detect symptoms of fault.
Abstract: A system and method for fault detection is provided. The fault detection system provides the ability to detect symptoms of fault in turbine engines and other mechanical systems that have nonlinear relationships. The fault detection system uses a neural network to perform a data representation and feature extraction where the extracted features are analogous to principal components derived in a principal component analysis. This neural network data representation analysis can then be used to determine the likelihood of a fault in the system.

Proceedings ArticleDOI
06 Jun 2005
TL;DR: In this article, the authors have discussed and shown that location and numbers of Fault Indicator (FIs) have an effect on distribution reliability indices such as SAIFI, SAIDI, CAIFI.
Abstract: SUMMARY Reduction of failure rates and applying effective fault management can be affected in improvement of reliability indices in distribution systems. One of the ways to improving the reliability of distribution networks in fault management procedure is installing Fault Indicators (FIs) in overhead primary networks. FIs allow operators to quickly identify the location of a fault on overhead lines feeders. FIs can reduce fault localization and therefore reduction in outage duration and outage cost. In this paper, modelling of FIs in reliability assessment and computing of related indices such as SAIFI, SAIDI, CAIFI is introduced. Using model development and case studies it is discussed and shown that location and numbers of FIs effect in distribution reliability indices.

Patent
14 Feb 2005
TL;DR: In this paper, a fault detection system for turbine engines is presented, which includes a feature extractor that extracts salient features from the selected sensor data and passes them to a classifier that analyzes the extracted salient features to determine if a fault is occurring or has occurred in the turbine engine fuel system.
Abstract: A system and method is provided that facilitates improved fault detection. The fault detection system provides the ability to detect symptoms of fault in the fuel system of a turbine engine. The fault detection system captures selected data from the turbine engines that is used to characterize the performance of the fuel system. The fault detection system includes a feature extractor that extracts salient features from the selected sensor data. The extracted salient features are passed to a classifier that analyzes the extracted salient features to determine if a fault is occurring or has occurred in the turbine engine fuel system. Detected faults can then be passed to a diagnostic system where they can be passed as appropriate to maintenance personnel.

Proceedings ArticleDOI
08 Nov 2005
TL;DR: This paper introduces a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis, and transforms the transistor level circuit description to a gate level description where stuck- open faults are represented by stuck- at faults.
Abstract: While most of the fault diagnosis tools are based on gate level fault models, for instance the stuck-at model, many faults are actually at the transistor level. The stuck-open fault is one example. In this paper we introduce a method which extends the use of available gate level stuck-at fault diagnosis tools to stuck-open fault diagnosis. The method transforms the transistor level circuit description to a gate level description where stuck-open faults are represented by stuck-at faults, so that the stuck-open faults can be diagnosed directly by any of the stuck-at fault diagnosis tools. The transformation is only performed on selected gates and thus has little extra computational cost. This method also applies to the diagnosis of multiple stuck-open faults within a gate. Successful diagnosis results are presented using wafer test data and an internal diagnosis tool from Philips

Journal ArticleDOI
TL;DR: In this article, a fault detection concept for line protection is presented, in which the difference and average quantities for phase active and reactive power entering and leaving the line are compared, and performance of the developed detector is computed under sampling misalignment as compared with conventional current differential approach.
Abstract: In this paper, investigation of a novel fault detection concept for line protection is presented. In this concept, the difference and average quantities for phase active and reactive power entering and leaving the line are compared. Performance of the developed detector is computed under sampling misalignment as compared with conventional current differential approach. This computation is carried out via simulating a tie line connecting two power system networks using the Electromagnetic Transient Program (EMTP). The detector sensitivity for internal fault and stability for external fault are examined for wide range of fault resistance and operating conditions. The test results show distinguished performance of the proposed power differential concept in detecting high impedance faults and remarkable stability during system severe power swings.

Proceedings ArticleDOI
12 Jun 2005
TL;DR: In this article, an optimization method of fault indicator placement by genetic algorithms is presented, where requirements such as the network structure with switchgear system, reliability factor, economic parameters and fault localization by switchgear can be taken into account in an objective function to minimize.
Abstract: This paper presents an optimization method of fault indicator placement by genetic algorithms. Requirements such as the network structure with switchgear system, reliability factor, economic parameters and fault localization by switchgear can be taken into account in an objective function to minimize. The influence of dispersed generation, inserted in the distribution network, on the fault indicator placement is also carried out. The tool created provides help to select the optimal fault indicator placement in the network following different objectives.

Journal ArticleDOI
14 Nov 2005
TL;DR: In this article, a general short-circuit analysis algorithm for three-phase four-wire distribution networks, based on the hybrid compensation method, is presented, where the neutral wire and assumed ground conductor are explicitly represented.
Abstract: The neutral wire in most existing power flow and fault analysis software is usually merged into phase wires using Kron's reduction method. In some applications, such as fault analysis, fault location, power quality studies, safety analysis, loss analysis etc., knowledge of the neutral wire and ground currents and voltages could be of particular interest. A general short-circuit analysis algorithm for three-phase four-wire distribution networks, based on the hybrid compensation method, is presented. In this novel use of the technique, the neutral wire and assumed ground conductor are explicitly represented. A generalised fault analysis method is applied to the distribution network for conditions with and without embedded generation. Results obtained from several case studies on medium- and low-voltage test networks with unbalanced loads, for isolated and multi-grounded neutral scenarios, are presented and discussed. Simulation results show the effects of neutrals and system grounding on the operation of the distribution feeders.