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Fault indicator

About: Fault indicator is a research topic. Over the lifetime, 10057 publications have been published within this topic receiving 143482 citations. The topic is also known as: FCI & power line fault indicator.


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Patent
14 Feb 2005
TL;DR: In this paper, a fault detection system for turbine engines is presented, which includes a feature extractor that extracts salient features from the selected sensor data and passes them to a classifier that analyzes the extracted salient features to determine if a fault is occurring or has occurred in the turbine engine fuel system.
Abstract: A system and method is provided that facilitates improved fault detection. The fault detection system provides the ability to detect symptoms of fault in the fuel system of a turbine engine. The fault detection system captures selected data from the turbine engines that is used to characterize the performance of the fuel system. The fault detection system includes a feature extractor that extracts salient features from the selected sensor data. The extracted salient features are passed to a classifier that analyzes the extracted salient features to determine if a fault is occurring or has occurred in the turbine engine fuel system. Detected faults can then be passed to a diagnostic system where they can be passed as appropriate to maintenance personnel.

50 citations

Journal ArticleDOI
TL;DR: In this paper, a novel pilot protection principle for HVDC transmission line based on fault component current is proposed, which has no limitation to the sampling frequency and can effectively identify a fault, whether it occurs in the line or beyond the line, can be effectively identified only using the fault components current at both converter stations.
Abstract: For high-voltage direct current (HVDC) transmission systems, the transient fault current characteristics are that: if the fault point is over the line, the fault component current measured at both converter stations would be increased and they have the same changing direction. If the fault point is beyond the line, the fault component current measured at one converter station is increasing and the fault component current measured at the other converter station is decreasing, so they have the opposite changing direction. According to this characteristic, a novel pilot protection principle for HVDC transmission line based on fault component current is proposed here. The principle proposed has no limitation to the sampling frequency. A fault, whether it occurs in the line or beyond the line, can be effectively identified only using the fault component current at both converter stations. At the same time, the setting criterion of the fault component current is also given. The simulation results show that the new method can identify the faults reliably and rapidly. The study is promising to have significant theoretical and practical value.

50 citations

Journal ArticleDOI
TL;DR: In this paper, the authors present fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals, and a test case with the exact fault location is presented.
Abstract: The authors present digital fault location techniques for transmission systems when digital fault recorded data are available at one terminal or two terminals. The systems under consideration are a 115 kV loop transmission system with data available at two terminals and a 69 kV radial transmission system with data available at one terminal. The data under consideration were recorded using digital fault recorders. The conversion of the data to workable data files and the techniques developed to achieve the highest accuracy in determining the fault location are discussed. Intermediate load buses and loads are considered in determining the fault location. An example of the effect of neglecting the presence of these loads is discussed. The fault location techniques are based on both the apparent impedance concept and the use of the three-phase voltage and current phasors. A test case with the exact fault location is presented. The techniques were developed on an IBM PC. >

50 citations

PatentDOI
19 Oct 1995
TL;DR: A successful method of defect isolation using scan-path testing in conjunction with electron beam probing for isolating various defects on devices with multi-layer (3+) metallization, 500 K usable gates and 2000 scan elements is presented.
Abstract: A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

50 citations

Proceedings ArticleDOI
03 Apr 2012
TL;DR: In this article, the dynamic performance of VSC-HVDC system integrated with a resistive superconducting fault current limiter is evaluated in PSCAD/EMTDC environment.
Abstract: Voltage source converter based HVDC systems involving overhead transmission lines are prone to severe over-voltages during line faults. At present, they find applications only in back to back and/or underground cable transmission, with low power ratings. A conventional HVDC system suppresses the dc fault very well with the controllers and smoothing reactors while the same is not true with voltage source converter based HVDC systems. This necessitates the operation of some kind of protective devices. A superconducting fault current limiter, in this regard, is a possible device which can mitigate the effects of dc line faults. In this work, it is aimed to evaluate the dynamic performance of VSC-HVDC system integrated with a superconducting fault current limiter. The resistive superconducting fault current limiter is modeled in MATLAB and is interfaced with low voltage VSC-HVDC system, in PSCAD/EMTDC environment. The results of analysis for various ac and dc fault conditions are presented.

50 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202381
2022215
202127
202061
2019116
2018160